Three-dimensional heterogeneous integrated chip of integrated circuit, and packaging method
A technology of integrated circuits and integrated chips, applied in circuits, electrical components, electrical solid-state devices, etc., can solve problems such as incompatibility of CMOS processes
Pending Publication Date: 2020-08-21
PEKING UNIV SHENZHEN GRADUATE SCHOOL
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Problems solved by technology
Monolithic heteroepitaxial growth technology is to epitaxially grow high-quality III-V devices on a template layer composed of buried III-V compounds, but this integration method is not compatible with standard CMOS processes
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Embodiment 2
[0054] Embodiment two: refer to image 3 and Figure 6 , the embodiment of the present invention discloses an integrated circuit three-dimensional heterogeneous integrated chip, including: a final substrate 23, a bonding layer 31 is provided on the final substrate 23, and several heterogeneous substrates are provided on the side of the bonding layer 31 away from the final substrate 23 integration layer;
[0055] refer to Figure 5 and Figure 6 , the heterogeneous integration layer includes: a first auxiliary substrate wafer 21, an IC device 1 and a filling layer 33; the first auxiliary substrate wafer 21 is disposed on the end of the bonding layer 31 away from the final substrate 23; the IC device 1 is disposed on On the first auxiliary substrate wafer 21; the filling layer 33 is wrapped in the bonding layer 31 (refer to image 3 ) surface, the first auxiliary substrate wafer 21 and the IC device 1. A wiring hole is opened on the heterogeneous integration layer, and the ...
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The invention discloses an integrated circuit three-dimensional heterogeneous integrated chip and a packaging method. The method comprises the steps: enabling different IC devices to be bonded on a first auxiliary substrate wafer through a temporary bonding technology, and enabling the IC devices and the first auxiliary substrate wafer to be bonded on a second auxiliary substrate wafer through a bonding layer; thinning the first auxiliary substrate wafer; bonding the IC device on the second auxiliary substrate wafer on the final substrate by using a wafer-level bonding technology, and removingthe second auxiliary substrate wafer; filling an organic matter between the IC device and the first auxiliary substrate wafer; repeating the above operations to form a plurality of heterogeneous integrated layers, arranging wiring holes connected with the IC device on the filling layer, and realizing electrical interconnection of the plurality of heterogeneous integrated layers through electric wires; and removing the redundant final substrate, scribing, and packaging. According to the integrated three-dimensional heterogeneous integrated chip, the manufacturing difficulty of the three-dimensional stacked chip is effectively reduced, and the performance of more resource concentration devices is improved, so that the three-dimensional heterogeneous integrated chip with high manufacturability, high performance and high stability is realized.
Description
technical field [0001] The invention relates to the field of heterogeneous chip recombination wafer transfer technology, in particular to an integrated circuit three-dimensional heterogeneous integrated chip and a packaging method. Background technique [0002] At present, mainstream heterogeneous integration technologies include monolithic heterogeneous epitaxial growth technology, epitaxial layer transfer technology, and small chip micron-scale assembly technology. Monolithic heteroepitaxial growth technology is to epitaxially grow high-quality III-V devices on a template layer composed of buried III-V compounds, but this integration method is not compatible with standard CMOS processes. A typical process of epitaxial layer transfer technology is to epitaxially grow InP double heterojunction on the InP substrate, guard against the optical epitaxial layer, and then transfer and bond the epitaxial layer with the InP substrate removed to the silicon with the adhesive layer th...
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IPC IPC(8): H01L25/065
CPCH01L25/0652H01L2225/06541
Inventor 金玉丰马盛林孙允恒
Owner PEKING UNIV SHENZHEN GRADUATE SCHOOL