Memory and forming method thereof

Abstract

The invention provides a memory and a forming method thereof. According to the bit lines in the memory, the width size of the first conductive layer is smaller than that of the second conductive layerabove the first conductive layer, so that the bottom interval size between the adjacent bit lines is larger than the top interval size of the adjacent bit lines. Thus, on the basis that the width size of the second conductive layer is met to guarantee the transmission performance of the bit lines, the bottom interval size between the adjacent bit lines is increased, and the bottom size of the storage node contact part filled between the adjacent bit lines can be further increased.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a memory and a forming method thereof. Background technique [0002] A memory typically includes a storage capacitor for storing charge representing stored information and a storage transistor connected to the storage capacitor. Also, there are usually multiple word lines and bit lines in the memory for controlling selected memory transistors. [0003] figure 1 is a schematic diagram of the existing memory structure, such as figure 1 As shown, in the existing memory, the bit line BL includes a plurality of film layers stacked in sequence from bottom to top, and the width of each film layer is uniform. Specifically, when forming the bit line BL, it is based on the same mask pattern layer, and usually anisotropic etching process is used to etch each film layer, so that the pattern in the mask pattern layer can be accurately copied to each in the film layer. [0004] How...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a memory to solve the problem that the existing memory is difficult to balance when facing the transmission performance of the bit line and the spacing size between adjacent bit lines

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