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Memory and method of forming the same

A memory and dielectric layer technology, applied in the direction of semiconductor devices, electrical solid devices, electrical components, etc., can solve the problems of large substrate application, large internal stress, semiconductor structure bending, etc., to improve the warping of the film layer and reduce the overall Effects of stress, size increase

Active Publication Date: 2022-05-31
FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the thickness of the interlayer dielectric layer is generally thick and has a relatively large internal stress, so that a correspondingly large stress is applied to the substrate, and the entire semiconductor structure is easily bent.

Method used

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  • Memory and method of forming the same
  • Memory and method of forming the same
  • Memory and method of forming the same

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0053] figure 1 is the layout structure of the memory in the first embodiment of the present invention, figure 2 for figure 1 It is a schematic cross-sectional view of the memory in the aa' direction in the first embodiment of the present invention.

[0054] combine figure 1 and figure 2 As shown, the memory in this embodiment includes: a substrate 100; a plurality of word lines 200 buried in the substrate 100; a dielectric stack layer 500 formed on the top surface of the substrate 100; The dielectric stack layer 500 has contact plugs 300 electrically connected to the word lines 200 .

[0055] The substrate 100 has a memory area 100A and a peripheral area 100B, and the peripheral area 100B is located at the periphery of the memory area 100A. And, a plurality of active areas AA are formed in the memory area 100A of the substrate 100 , and the plurality of active areas AA are arranged in an array to form a memory cell array.

[0056] continue to refer to figure 1As show...

Embodiment 2

[0088] The difference from the first embodiment is that, in this embodiment, the plurality of contact plugs in the peripheral region on the same side of the memory region are staggered in the arrangement direction of the word lines instead of being completely aligned.

[0089] image 3 is the layout structure of the memory in the second embodiment of the present invention, such as image 3 As shown, the memory includes M word lines 200, and the M word lines 200 are sequentially arranged along the first direction (X direction), wherein M is a positive integer greater than 1.

[0090] Further, contact plugs connected to the Nth word line are formed on the second end portion (not shown in the figure), and contact plugs 300 ′ connected to the N−1th word line and to the N+th word line are formed. The contact plugs 300 ′ connected to one word line are all formed on the first end portion, wherein N is a positive integer greater than 1 and less than M. That is, similar to the first ...

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Abstract

The invention provides a memory and its forming method. Extending the end of the word line into the peripheral area, and forming a contact plug in the peripheral area to be electrically connected to the end of the word line, so that the space in the peripheral area can be fully utilized to prepare the contact plug in the peripheral area , which is conducive to increasing the size of each contact plug, effectively reducing the difficulty of manufacturing the contact plug, and correspondingly improving the connection performance between the contact plug and the word line. Moreover, the present invention also enables the dielectric layer formed on the substrate to appear as a stacked layer with multiple film layers, thereby helping to reduce the stress of the formed dielectric stacked layer.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to a memory and a method for forming the same. Background technique [0002] A memory (eg, dynamic random access memory, Dynamic Random Access Memory) generally has a memory cell array, and the memory cell array includes a plurality of memory cells arranged in an array. And, the memory also has a plurality of word lines, and each word line is electrically connected to a corresponding memory cell, so as to apply a corresponding signal to each memory cell. [0003] Wherein, for each word line, it is usually necessary to form a corresponding contact plug, so as to realize the electrical extraction of each word line. Specifically, the bottom of the contact plug formed in the interlayer dielectric layer is connected to the word line, and the top of the contact plug extends out of the interlayer dielectric layer for connection with external signals. At present, the t...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108
CPCH10B12/01H10B12/30H10B12/48H10B12/09
Inventor 詹益旺李甫哲林刚毅黄永泰童宇诚蔡振文
Owner FUJIAN JINHUA INTEGRATED CIRCUIT CO LTD