280results about How to "Simple forming process" patented technology

The invention discloses a high-entropy alloy particle reinforced aluminum base composite material and a stirring casting preparation process thereof. The preparation process adopts mechanical alloying to prepare high-entropy alloy powder and screen to obtain high-entropy alloy particles; the high-entropy alloy particles are sealed by adopting an aluminum alloy pipe having the same material with a basal body; the aluminum alloy pipe weighed in a segmented manner is added in the molten basal body; the high-entropy alloy particles are dispersed by a stirring mode; and the high-entropy alloy particle reinforced aluminum base composite material is prepared by a casting process. The high-entropy alloy particles are 0.1-35%; aluminum alloys are 65-99.9%; and the sum of the two is 1. The high-entropy alloy particles in the structure of the prepared composite material are uniformly dispersed; the high-entropy alloy and aluminum alloy interface bonding compatibility is excellent; the strength and the toughness are excellent; the preparation process is simple; the powder has no need to be treated; the cost is low; the stability is good; and the composite material is suitable for large-batch production and standard production, and is excellent in promotion and application prospect.

The invention provides a chambering -forging forming method for an aluminum alloy hub with a complex structure and a die thereof. The forming method comprises the steps of: preparing for materials; heating blanks; upsetting; mould-pressing and chambering a rim. The die for realizing the chambering-forging forming method for the aluminum alloy hub with the complex structure comprises a forging die and a rim-chambering die, wherein an upper die of the forging die consists of an upper die body and an upper die core which are sequentially nested and mounted, a lower die consists of a lower die body, a lower die core and an ejector rod which are sequentially nested and mounted; and the bottom and the side wall of the assembling part of the lower die core and the lower die body are uniformly provided with 4-8 R3 penetrating exhaust grooves, the rim-chambering die consists of an upper chambering die and a lower chambering die, and the size of a cavity of the upper chambering die is same as the size of the cavity of the upper die core of the forging die. The invention realizes once-heating forming; a non-burr forging and rim-chambering forming process is adopted, thus two trimming procedures are eliminated, material utilization rate is improved, and number of equipment is reduced; and the rim-chambering die has a simple structure and is convenient for operation.

The invention discloses a production method of a graphene-aluminum composite, and belongs to the field of metal-matrix composites. Aluminum alloy powder with the semisolid temperature interval and graphene are adopted as raw materials. The method mainly includes the steps of 1, chemical nickel plating of the graphene; 2, mixing; 3, pressing; and 4, semisolid extruding. According to the graphene-aluminum composite produced through the method, the wettability and the metallurgical bonding strength of the nickel-plated graphene and aluminum alloy are high, the nickel-plated graphene is uniformly distributed in the matrix aluminum alloy, the microstructure is compact, the specific strength and the specific stiffness are high, and the thermal conductivity and the electrical conductivity are good. Thus, the graphene-aluminum composite has wide application prospects in the fields of the national defense and military industry, aerospace, electricity and heat exchange.

The invention discloses an infrared image sensor and a forming method thereof. The method comprises the steps of providing a substrate with a CMOS (Complementary Metal-Oxide-Semiconductor Transistor) control circuit, forming a pixel structure and a plug for electrically connecting the pixel structure with the control circuit on the substrate, also forming a first sacrifice layer between the pixel structure and the substrate, forming a second sacrifice layer with a first opening and covering the second sacrifice layer on the pixel structure, with the first opening being above the plug, forming a supporting layer on the second sacrifice layer on the side wall and the bottom of the first opening, forming a second opening in the supporting layer, removing the first sacrifice layer and the second sacrifice layer through the second opening, forming a covering layer which is a transmission layer for infrared ray after the first sacrifice layer and the second sacrifice layer are removed, covering the covering layer on the supporting layer, packing the first opening and the second opening, forming a third opening between the covering layer and the supporting layer, and forming a sealing layer in the third opening through a physical vapor deposition technology, so as to seal the third opening. The covering technology in the technical scheme is compatible with the traditional semiconductor technology.

The invention provides a chip packaging method and a chip packaging structure, wherein the chip packaging method comprises the steps of providing a first chip which comprises a first surface and a second surface that oppose each other, wherein the first surface of the first chip is provided with a plurality of first pads; providing a second chip with a third surface and a fourth surface that oppose each other, wherein the third surface of the second chip is provided with a plurality of second pads and the area of the second chip is larger than that of the first chip; providing a carrier plate; combining the fourth surface of the second chip with the surface of the carrier plate, wherein the plurality of second pads are arranged outside the combining area between the first chip and the second chip; forming a sealing material layer on the surface of the carrier plate, wherein the sealing material layer packages the first chip and the second chip; and forming a first conductive structure and a second conductive structure in the sealing material layer, wherein the first conductive structure is electrically connected with the first pads and the second conductive structure is electrically connected with the second pads. A package which is formed according to the chip packaging method has advantages of reduced structural dimension, improved stability and improved reliability.

The invention provides a color filter which comprises a base plate, black matrixes and color resistance layers, wherein the black matrixes are arranged on the surface of the base plate and are in lattice structures, the black matrixes are at intervals and are exposed out of the surface of the base plate, and the sections of the black matrixes between adjacent intervals vertical to the base plate is in the shape of a Chinese character TU (convex) with a low edge and a high central part; and the color resistance layers are arranged on the surfaces of the base plate at the intervals and are superposed with the edges of the black matrixes between the adjacent intervals. The invention further provides a forming method of the color filter. According to the forming method of the color filter, a black matrix is formed by utilizing a half-gray mask plate so that an ox horn can be reduced, even eliminated, and the light leakage of pixel edge of a display device is prevented; and the forming process is simple and the contrast ratio of the display is high.

The invention provides a processing mould and a processing method of an inverted glass plate. The inverted glass plate comprises a main body part, a transitional part and a stretching part, wherein the stretching part comprises a first outer surface back away from an accommodating space; the first outer surface comprises a first end point away from the main body part and a connecting point connected with the transitional part; the first outer surface is vertical to the horizontal direction in the tangent direction of the connecting point; an included angle between the tangent direction of thefirst end point and the horizontal direction and away from the accommodating space is theta, and theta is greater than 90 degrees and equal to and smaller than 180 degrees; and the horizontal distancebetween the connecting point and the first end point is U. The processing mould comprises a lower mould with a mould cavity and an upper mould matched with the lower mould, wherein the lower mould comprises a bottom wall and a side wall which are matched to define the mould cavity; the upper mould comprises a bulge; during mould closing, the bulge stretches into the mould cavity and is spaced from the side wall; and the space between the bulge and the side wall is greater than or equal to the sum of the thickness of the stretching part and the distance U and is smaller than or equal to doubleof the sum of the thickness of the stretching part and the distance U.

Provided is a method for forming a self-aligned triple pattern. The method comprises: providing a layer to be etched, wherein the surface of the layer to be etched is equipped with a discrete first sacrificial layer; forming a second sacrificial film on the surface of the layer to be etched and the sidewall and the top of the first sacrificial layer and forming a first sidewall layer on the surface of the second sacrificial film; planarizing the second sacrificial film and the first sidewall layer until the top surface of the first sacrificial layer is exposed, the first sidewall layer forms a first sidewall, the second sacrificial film forms a second sacrificial layer, and the tops surfaces of the second sacrificial layer and the first sidewall are aligned to the top surface of the first sacrificial layer; removing the first sacrificial layer after a planarization process is executed; forming a second sidewall on the surface of the layer to be etched on the two sides of the second sacrificial layer and the first sidewall; dry etching the second sacrificial layer by using the first sidewall and the second sidewall as a mask until the surface of the layer to be etched is exposed. A formed self-aligned triple pattern has a small size and a simple forming process.

Provided is a structure of an organic EL element capable of reducing the product cost by drastically simplifying the fabrication process as compared with a conventional multi-photon organic EL element. An insulating organic layer having a low dielectric constant is interposed to smooth the transfer of electron charges between a strong electron-accepting material and an electron transport layer included in a charge generation layer of the conventional multi-photon organic EL element.

The invention discloses a laterally diffused metal oxide semiconductor (LDMOS) transistor and a formation method thereof. The formation method for the LDMOS transistor comprises the following steps of: providing a semiconductor substrate, and forming a well region of a first conduction type in the semiconductor substrate; forming a heavily doped region of the first conduction type in the well region, and forming drift regions of a second conduction type in the well region at both sides of the heavily doped region; respectively forming drain regions of the second conduction type in the drift regions; forming a separator of the first conduction type in the heavily doped region, and forming source regions of the second conduction type in the heavily doped region at both sides of the separator; and forming metal plugs respectively connected with the source regions on the semiconductor substrate. The LDMOS transistor formed by the invention is wider in safe working range and low in resistance and internal friction under the same area.

A method for forming a semiconductor device comprises a step of providing a substrate whose surface has gate structures, wherein two sides of each gate structure has an interconnection region respectively, portions, in the interconnection regions, of the substrate have source regions and drain regions positioned at two sides of the corresponding gate structure respectively, and surfaces of the substrate and the gate structures have a first dielectric layer; a step of forming a barrier layer on the surface of the first dielectric layer, wherein the material of the barrier layer is different from that of the first dielectric layer, and the pattern of the barrier layer at least penetrates one interconnection region; a step of forming a first patterned layer with a first opening on the first dielectric layer and the surface of the barrier layer, wherein the first opening exposes the positions of the interconnection regions; a step of taking the first patterned layer and the barrier layer as mask layers, and etching the first dielectric layer until the surface of the substrate in the interconnection regions is exposed, so as to form source-drain grooves; a step of forming gate through holes in the first dielectric layer for exposing tops of the gate structures; and a step of forming source-drain conductive structures in the source-drain grooves and forming gate plugs in the gate through holes. The formed semiconductor device is good in appearance and has improved performances.

The invention provides a semiconductor structure and a formation method thereof. The semiconductor structure comprises a substrate; a first gate structure which is arranged on the surface of the substrate of the first regional part, wherein the first gate structure comprises a first work function layer; a second gate structure which is arranged on the surface of the substrate of the second regional part, wherein the second gate structure comprises a second work function layer, and the work function type of the second work function layer is different from the work function type of the first work function layer; an insulating layer which is arranged on the surface of the substrate of the third regional part, wherein the insulating layer covers the surface of the side wall of the first gate structure and the surface of the side wall of the second gate structure; an upper dielectric layer which is arranged on the top surface of the first gate structure, the top surface of the second gate structure and the top surface of the insulating layer; an opening which is arranged in the upper dielectric layer, wherein the top part of a first metal gate, the top part of a second metal gate and the top part of the insulating layer are exposed out of the bottom part of the opening; and a conductive layer which fully fills the opening, wherein the conductive layer is electrically connected with the first metal gate and the second metal gate. The electrical performance of the semiconductor structure can be improved by the semiconductor structure and the formation method thereof.

The invention belongs to the technical field of high-entropy alloys and discloses a high-melting-point high-entropy alloy NbMoTaWVTi and a preparation method of the high-melting-point high-entropy alloy NbMoTaWVTi. According to the method, a forming method that a mechanical alloying technology and a spark plasma sintering technology are combined is adopted. Compared with a traditional vacuum arc furnace casting method, by the adoption of the preparation method, operation is easier and more convenient, the temperature required in forming is lowered greatly, sintering time is short, a block material which is uniform in composition and near-total dense can be obtained through one-time sintering, and near-net forming is achieved; and the microscopic structure of the obtained alloy is characterized in that granular second phases are diffused and distributed in an isometric crystal matrix. By the adoption of the preparation method, the prepared alloy is uniform in structure and tiny in grain size and has higher strength and plasticity, and the optimum mechanical performance meets the conditions that compression yield strength is 2,709.2 MPa, the maximum compressive strength is 3,114.9 MPa, and the plasticity dependent variable generated in fracture is 7.5%.

The invention relates to a medical biological tissue structure and a preparation method and a special device of the medical biological tissue structure, and belongs to the technical field of biology, medical treatment and medical instruments. The medical biological tissue structure comprises a hollow pipe, a functional layer and a synthetic macromolecule protective film, wherein the hollow pipe is made of biological materials containing cells or being free of the cells, and the functional layer is attached to the hollow pipe and contains or does not contain the cells. The medical biological tissue structure, the preparation method and the special device are based on the attachment cross-linking and solidity principle, under control of a computer, the hollow pipe is firstly extruded out through a special spraying nozzle, then the biological materials are sprayed and attached to the hollow pipe to form the functional layer and accumulated layer by layer to form a composite molding body, and finally a synthetic macromolecule solution is sprayed to the outer surface of the composite molding body to form the protective film. According to the set molding steps, a three-dimensional structure body which contains synthetic macromolecule materials, the cells and the natural biological materials is finally manufactured, has the space complex shape and is of the gap structure is finally manufactured. The medical biological tissue structure can be molded at the normal temperature, the process is simple, the cell survival rate is high, distribution is even and controllable, and the good mechanical property and the good biological property are achieved.

The invention discloses a manufacturing method for semiconductor device of metal oxide, which comprises: forming dielectric layer on the semiconductor underlay; forming polycrystalline silicon layer on the said dielectric layer; forming hard mask layer on the said polycrystalline silicon layer and patterning it; etching the said polycrystalline silicon layer for the mask layer by the said hard mask layer to form grid; forming the protective layer on the grid surface; etching the said protective layer by etching method; eliminating the said hard mask layer. The invention forms a sidewall protective layer in the said side wall of the grid, which has the function of separating the corrosive liquid from grid, thus to avoid bottleneck.

The invention relates to an air pressure forming method of an infrared heating metal foil plate and a device; wherein, the method includes the steps of accurately heating a metal foil plate with an infrared heat source, applying pressure to the softened metal foil plate with high pressure gas and realizing the precise forming of the metal foil plate by matching a micro mold; the device consists of a bottom plate, an upper pressure plate, a micro mold, a gas pressure nozzle, a three-dimensional mobile platform, a three-dimensional mobile platform controller, an air compressor, a computer, a drive, an infrared radiation thermometer, a three-dimensional worktable and an infrared focusing heating device. The method and the device integrates the technologies of infrared heating, infrared temperature measurement and air pressure forming to a micro-forming process, thus improving the forming performance of the metal foil plate, ensuring the quality of the surfaces of work pieces; the high pressure gas is used for replacing a male mold, thus simplifying the technique, causing the loading pressure to be more even and strengthening the filling ability; the method and the device can realize the low cost and mass production of the metal foil plate by combining an array female mold.

The invention discloses a novel hollow sodium-filled valve. The novel hollow sodium-filled valve comprises a valve shell and a solid rod part. The forming method of the valve shell comprises the steps that cross wedge rolling is performed on a steel pipe material for preforming; friction welding sealing is performed on the head of a preformed billet; afterwards, a die forging forming technology is performed, so the valve shell is integrally formed. The valve shell comprises a flared hollow disc part and a hollow rod part which are integrally formed. One end of the hollow rod part is welded to the solid rod part through friction welding, and the diameter of the cross section of the solid rod part is equal to the outer diameter of the cross section of the hollow rod part. The disc end face of the hollow disc part is airtight, and an inner cavity is defined by the disc end face of the hollow disc part, the hollow rod part and the solid rod part and is filled with sodium. The novel hollow sodium-filled valve is convenient to form, capable of saving materials and good in heat dissipation performance.

The invention discloses a circuit substrate and its formation method and semiconductor encapsulation. The circuit substrate includes a substrate body having a first terminal and a second terminal separated from the first terminal. A circuit wire includes a wiring unit for electrically connecting the first and second terminals by electrically connecting conductive polarization particles that include a first polarity and a second polarity that is opposite to the first polarity. The circuit wire also includes an insulation unit for insulating the wiring unit.

A solid-state image pickup apparatus includes an image pickup pixel and a focus detection pixel. The image pickup pixel includes a micro lens and a photoelectric conversion unit that receives light incident from the micro lens. The focus detection pixel includes the micro lens, the photoelectric conversion unit, and a light shielding unit that shields part of light incident on the photoelectric conversion unit. In the solid-state image pickup apparatus, the micro lens is uniformly formed in the image pickup pixel and the focus detection pixel, and the focus detection pixel further includes a high refractive index film formed under the micro lens.

A method for forming a semiconductor device comprises a step of providing a substrate whose surface has gate structures, wherein two sides of each gate structure has an interconnection region respectively, portions, in the interconnection regions, of the substrate have source regions and drain regions positioned at two sides of the corresponding gate structure respectively, and surfaces of the substrate and the gate structures have a first dielectric layer; a step of forming a barrier opening on the surface of the first dielectric layer, wherein the pattern of the barrier opening at least penetrates one interconnection region; a step of forming a barrier layer in the barrier opening; a step of forming a first patterned layer on the first dielectric layer and the surface of the barrier layer, wherein the first patterned layer exposes the positions of the interconnection regions; a step of taking the first patterned layer and the barrier layer as mask layers, and etching the first dielectric layer until the surface of the substrate in the interconnection regions is exposed, so as to form source-drain grooves; a step of forming gate through holes in the first dielectric layer for exposing tops of the gate structures; and a step of forming source-drain conductive structures in the source-drain grooves and forming gate plugs in the gate through holes. The formed semiconductor device is good in appearance and has improved performances.

The invention provides a formation method for a VDMOS (vertical double-diffused metal oxide semiconductor) device, which comprises the following steps: providing a semiconductor substrate and forming an epitaxial layer on the semiconductor substrate; forming a sacrificial layer with an opening on the surface of the epitaxial layer, wherein the opening is exposed out of the surface of the epitaxial layer; thermally oxidizing the epitaxial layer in the opening so as to form a first grid electrode oxidation layer; removing the sacrificial layer; thermally oxidizing the epitaxial layer so as to form a second oxidation layer; depositing a polycrystalline silicon layer which covers the first grid electrode oxidation layer and the second oxidation layer; etching the polycrstaslline silicon layer and the second oxidation layer so as to form a grid electrode structure; and forming a source region, a source electrode metal layer, a drain electrode metal layer and a grid electrode metal layer. The formation method reduces the technology difficulty of the grid electrode oxidation layer and increases the thickness of the grid electrode oxidation layer between a drain electrode and a grid electrode, so as to reduce the capacitance value between the grid electrode and the drain electrode and increase the switching speed of the VDMOS.