Semiconductor structure and formation method thereof

A semiconductor and gate structure technology, applied in the field of semiconductor structure and its formation, can solve the problems of semiconductor structure electrical performance to be improved, and achieve the effect of simple formation process and saving process steps

Active Publication Date: 2017-04-05
SEMICON MFG INT (SHANGHAI) CORP +1
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  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Although the introduction of high-k metal gates can improve the electrical properties of semiconductor structures to a certain extent, the electrical properties of semiconductor structures formed by existing technologies still need to be improved.

Method used

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  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof
  • Semiconductor structure and formation method thereof

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Embodiment Construction

[0021] It can be seen from the background art that the electrical performance of the semiconductor structure formed in the prior art needs to be improved.

[0022] It has been found through research that in order to simultaneously meet the requirements of improving the threshold voltage (ThresholdVoltage) of NMOS transistors and PMOS transistors, different metal materials are usually used as the work function (WF, Work Function) layer materials in the gate structures of NMOS transistors and PMOS transistors, The material of the work function layer in the NMOS tube may be called an N-type work function material, and the material of the work function layer in the PMOS tube may be called a P-type work function material. When the NMOS transistor and the PMOS transistor share the same metal gate, there will be an N / P boundary Interface (N / P boundaryInterface) between the N-type work function layer and the P-type work function layer at the junction of the NMOS transistor and the PMOS...

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Abstract

The invention provides a semiconductor structure and a formation method thereof. The semiconductor structure comprises a substrate; a first gate structure which is arranged on the surface of the substrate of the first regional part, wherein the first gate structure comprises a first work function layer; a second gate structure which is arranged on the surface of the substrate of the second regional part, wherein the second gate structure comprises a second work function layer, and the work function type of the second work function layer is different from the work function type of the first work function layer; an insulating layer which is arranged on the surface of the substrate of the third regional part, wherein the insulating layer covers the surface of the side wall of the first gate structure and the surface of the side wall of the second gate structure; an upper dielectric layer which is arranged on the top surface of the first gate structure, the top surface of the second gate structure and the top surface of the insulating layer; an opening which is arranged in the upper dielectric layer, wherein the top part of a first metal gate, the top part of a second metal gate and the top part of the insulating layer are exposed out of the bottom part of the opening; and a conductive layer which fully fills the opening, wherein the conductive layer is electrically connected with the first metal gate and the second metal gate. The electrical performance of the semiconductor structure can be improved by the semiconductor structure and the formation method thereof.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor structure and a forming method thereof. Background technique [0002] The main semiconductor device of an integrated circuit, especially a very large scale integrated circuit, is a metal-oxide-semiconductor field effect transistor (MOS transistor). With the continuous development of integrated circuit manufacturing technology, the technology nodes of semiconductor devices are continuously reduced, and the geometric dimensions of semiconductor structures are continuously reduced following Moore's law. When the size of the semiconductor structure is reduced to a certain extent, various secondary effects caused by the physical limit of the semiconductor structure appear one after another, and it becomes more and more difficult to scale down the feature size of the semiconductor structure. Among them, in the field of semiconductor manufacturing, t...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H01L29/06
CPCH01L29/0649H10B10/12
Inventor 李勇
Owner SEMICON MFG INT (SHANGHAI) CORP
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