Chip packaging method and chip packaging structure

Abstract

The invention provides a chip packaging method and a chip packaging structure, wherein the chip packaging method comprises the steps of providing a first chip which comprises a first surface and a second surface that oppose each other, wherein the first surface of the first chip is provided with a plurality of first pads; providing a second chip with a third surface and a fourth surface that oppose each other, wherein the third surface of the second chip is provided with a plurality of second pads and the area of the second chip is larger than that of the first chip; providing a carrier plate; combining the fourth surface of the second chip with the surface of the carrier plate, wherein the plurality of second pads are arranged outside the combining area between the first chip and the second chip; forming a sealing material layer on the surface of the carrier plate, wherein the sealing material layer packages the first chip and the second chip; and forming a first conductive structure and a second conductive structure in the sealing material layer, wherein the first conductive structure is electrically connected with the first pads and the second conductive structure is electrically connected with the second pads. A package which is formed according to the chip packaging method has advantages of reduced structural dimension, improved stability and improved reliability.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a chip packaging method and a chip packaging structure. Background technique [0002] Wafer Level Chip Size Packaging (WLCSP) technology is a technology in which a wafer is packaged and tested and then cut to obtain a single finished chip. The size of the packaged chip is exactly the same as that of the bare chip. Wafer-level chip-scale packaging technology has completely subverted traditional packaging, such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier) and organic leadless chip carrier (Organic Leadless Chip Carrier), etc. , small, short, thin and low-cost requirements. The size of the chip packaged by the wafer-level chip size packaging technology can be highly miniaturized, and the cost of the chip is significantly reduced with the reduction of the chip size and the increase of the wafer size. Wafer-level chip-scale packaging technolog...

AI Technical Summary

Problems solved by technology

[0004] However, the packaging quality of the existing fan-out wafer level packaging method and the integration level of the formed packaging structure still need to be improved

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