Manufacturing method of metal oxide semiconductor device

Abstract

The invention discloses a manufacturing method for semiconductor device of metal oxide, which comprises: forming dielectric layer on the semiconductor underlay; forming polycrystalline silicon layer on the said dielectric layer; forming hard mask layer on the said polycrystalline silicon layer and patterning it; etching the said polycrystalline silicon layer for the mask layer by the said hard mask layer to form grid; forming the protective layer on the grid surface; etching the said protective layer by etching method; eliminating the said hard mask layer. The invention forms a sidewall protective layer in the said side wall of the grid, which has the function of separating the corrosive liquid from grid, thus to avoid bottleneck.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a metal oxide semiconductor device. Background technique [0002] With the rapid development of semiconductor manufacturing technology, in order to achieve faster computing speed, larger data storage capacity and more functions of semiconductor devices, wafers are developing towards higher component density and high integration. Metal oxide semiconductor devices (MOS) gates are becoming thinner and shorter than before. The manufacturing technology of semiconductor devices has entered the 65nm or even 45nm process node, and the minimum feature size of the gate width has reached 45nm or smaller. [0003] In NMOS and PMOS transistors of complementary metal oxide semiconductor devices (CMOS), the preferred material for making the gate is polysilicon, which has special heat resistance and high etch pattern accuracy. During the process o...

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Problems solved by technology

Under this condition, when phosphoric acid is used to remove the hard mask, the phosphoric acid will simultaneously corrode the polysilicon gate portion doped with phosphorus impurities, resulting in the phenomenon of necking 160 shown in FIG. 3 on the polysilicon gate 150, especially in When the characteristic line width of the gate is below 65nm, as long as the time for removing the hard mask with phosphoric acid is a little longer for the extremely narrow gate, bottlenecks will easily occur

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