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No-load capacitance LDO circuit

A no-load, load current technology, applied in the direction of adjusting electrical variables, control/regulation systems, instruments, etc., can solve the problems of terminal voltage exceeding the withstand voltage value, small capacitance value, large feedback resistance, etc., to avoid overvoltage damage, Improved stability and reliability effects

Active Publication Date: 2020-09-11
SHENZHEN LONTIUM SEMICON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For example, when the external load block of the no-load capacitor LDO circuit is suddenly turned off first, but the no-load capacitor LDO circuit is not turned off temporarily, that is, when the main circuit of the LDO is not turned off temporarily, the original current drawn by the block suddenly stops drawing, so this part of the current is only It can be discharged through the feedback resistor, but because the feedback resistor is relatively large, and the load capacitor is on-chip, its capacitance value is very small, it is difficult to discharge and store such a large current in a short time, so it will be in the main circuit of the LDO The output terminal out produces a huge voltage jump; and because the load modules inside the no-load capacitor LDO circuit use 1.2V devices, this overshoot will cause the terminal voltage of the load module to exceed the withstand voltage value, causing reliability problems , making the LDO circuit unstable with no load capacitor

Method used

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Embodiment Construction

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0042] In this application, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes none. other elements specifically listed, or also include elements inher...

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Abstract

The invention provides a no-load capacitance LDO circuit. The circuit comprises a main circuit and an auxiliary module. The output end of the main circuit is used for outputting load current to a load; the auxiliary module is used for discharging the load current when the load stops receiving the load current and the main circuit still has output, so that the jump amplitude value of the output voltage of the main circuit is smaller than the preset voltage value. The no-load capacitance LDO circuitdoes not generate huge voltage jump, overvoltage damage to devices in the no-load capacitance LDOcircuit is avoided, and therefore the stability and the reliability of the no-load capacitance LDO circuit are improved.

Description

technical field [0001] The invention belongs to the technical field of semiconductor integrated circuits, and more specifically relates to a no-load capacitor LDO circuit. Background technique [0002] With the development of technology, low power supply voltage has become a trend in deep nano-micron technology. For example, the internal devices of LDO (low dropout regulator, low dropout linear regulator) will be powered by 1.2V power supply; due to the limitation of package PIN pin , the no-load capacitor LDO circuit is widely used, the no-load capacitor LDO circuit such as figure 1 As shown, it not only saves the PIN pin but also saves the area inside the chip. [0003] In actual use, if there is a problem with the timing control, it will cause the output voltage of the LDO main circuit to fluctuate. For example, when the external load block of the no-load capacitor LDO circuit is suddenly turned off first, but the no-load capacitor LDO circuit is not turned off temporar...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G05F1/56
CPCG05F1/561
Inventor 张亚南季翔宇陈余卫海燕付家喜邰连梁张永领
Owner SHENZHEN LONTIUM SEMICON TECH CO LTD
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