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Efficient test method based on hierarchical test vectors

A technology of test vectors and test methods, which is applied in the direction of measuring electricity, measuring devices, and measuring electrical variables, etc., can solve problems such as low efficiency, many internal connections, and complex structures, so as to reduce the number, speed up the test speed, and improve the test efficiency. Effect

Active Publication Date: 2020-09-29
WUXI ESIONTECH CO LTD
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AI Technical Summary

Problems solved by technology

The current mainstream test method is to use the walking-1 algorithm (serial shift method, or also called walking algorithm) to generate test vectors for testing. The structure is becoming more and more complex, and the internal wiring is usually more, so the efficiency of this test method is low

Method used

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  • Efficient test method based on hierarchical test vectors
  • Efficient test method based on hierarchical test vectors
  • Efficient test method based on hierarchical test vectors

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Embodiment Construction

[0026] The specific embodiments of the present invention will be further described below in conjunction with the accompanying drawings.

[0027] This application provides a high-efficiency testing method based on hierarchical test vectors, which is based on a stimulus generation circuit (TPG) to generate hierarchical test vectors to test the interconnection path to be tested, which is different from the conventional walking-1 algorithm. Test vectors, this kind of hierarchical test vectors can reduce the test vectors on the basis of ensuring 100% test coverage to speed up the test speed and improve the test efficiency. The method of this application is:

[0028]1. The interconnection paths to be tested are divided into layers according to the circuit structure to which the interconnection paths to be tested belong, and all the interconnection paths to be tested form K different hierarchical structures, K≥2. Each hierarchical structure includes several parallel structural units,...

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Abstract

The invention discloses an efficient test method based on hierarchical test vectors, relating to the technical field of chip testing. According to the method, a to-be-tested interconnection path is divided into a plurality of hierarchical structures; a test sequence is generated for each hierarchical structure; each test vector, corresponding to the same structural unit in the previous hierarchical structure, in each hierarchical structure is used as a test group to perform serial shift in sequence; the hierarchical test sequences are correspondingly generated according to the hierarchies of the interconnection paths, the number of the test sequences can be greatly reduced on the basis of ensuring full-coverage test, so that the test speed is increased, the test efficiency is improved, andthe method is particularly suitable for a structure containing a large number of interconnection paths, such as a multi-bare-chip FPGA.

Description

technical field [0001] The invention relates to the technical field of chip testing, in particular to an efficient testing method based on hierarchical testing vectors. Background technique [0002] In the field of chip production, in order to ensure the normal function of the chip, it is necessary to select tested components for packaging when the chip is packaged. At the same time, after the package is completed, it is still necessary to test the correctness of the internal wiring of the chip to ensure that the packaged chip functions normally. The current mainstream test method is to use the walking-1 algorithm (serial shift method, or also called walking algorithm) to generate test vectors for testing. The structure is also becoming more and more complex, and there are usually more internal wiring, so the efficiency of this testing method is low. Contents of the invention [0003] Aiming at the above problems and technical requirements, the present inventor proposes a...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28
CPCG01R31/2853
Inventor 单悦尔徐彦峰范继聪张艳飞闫华
Owner WUXI ESIONTECH CO LTD
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