Semiconductor structure and its preparation method

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method includes: providing a first semiconductor substrate, forming a contact sacrificial layer and a bottom layer of a gate, forming a channel structure, forming gate spacers and spacers with bottom openings layer, remove the contact sacrificial layer and the functional structure layer to expose the channel layer, and form a doped semiconductor layer. The semiconductor structure and its preparation method of the present invention remove the contact sacrificial layer based on the gate spacer to form an interlayer gap, and remove the functional structure layer based on the interlayer gap to expose the bottom epitaxial layer, and then deposit to form a doped semiconductor layer, and simultaneously realize The electrical extraction of the bottom epitaxial layer reduces the area of ​​the core region, so that insulating materials can be filled in the gate spacer to form an insulating filling layer, which solves the problem of gate word lines caused by filling metal conductive materials in the gate spacer. The leakage problem between the common source line and the common source line, and solve the problem of parasitic capacitance formed between the two. The invention also realizes doubling of pads in device structure preparation.

Description

Technical field [0001] The present invention belongs to the field of integrated circuit manufacturing techniques, and more particularly to a semiconductor structure and a preparation method thereof. Background technique [0002] With the development of planar flash memory, the production process of semiconductor has made great progress. However, in recent years, the development of flat flash memory has encountered various challenges: physical limit, existing development technology limit, and storage electronic density limit. In this context, in order to solve the difficulties encountered in flat flash, various three-dimensional (3D) flash memory structure appear to be born, for example, 3D NOR (3D or Nor) in various three-dimensional (3D) flash memory structure, for example, 3D NOR (3D or non) Flash and 3D NAND (3D and non) flash. However, in the three-dimensional memory structure, there is often a problem that the device core area is large, and the leakage and parasitic capacita...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and a preparation method thereof, which are used to solve the problem of large area occupied by the core area of ​​the preparation of the device structure and the gap between the gate word line and the common source line in the prior art. There are problems such as leakage and parasitic capacitance between the

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