Semiconductor structure and preparation method thereof

Abstract

The invention provides a semiconductor structure and a preparation method thereof. The preparation method comprises the steps of providing a first semiconductor substrate, forming a contact sacrificial layer and a gate bottom layer, forming a channel structure, forming a gate isolation groove and an isolation groove spacer layer with a bottom opening, removing the contact sacrificial layer and a functional structure layer to expose the channel layer, and forming a doped semiconductor layer. According to the semiconductor structure and a preparation method thereof, the contact sacrificial layeris removed based on the gate isolation groove to form an interlayer gap, the functional structure layer is removed based on the interlayer gap to expose the bottom epitaxial layer, and deposition isperformed to form a doped semiconductor layer. Meanwhile, electrical leading-out of the bottom epitaxial layer is achieved, the area of the core region is reduced, and therefore the gate isolation groove can be filled with insulating materials to form an insulating filling layer, the problem of electric leakage between the gate word line and the common source line due to the fact that the gate isolation groove is filled with metal conductive materials is solved, and the problem of parasitic capacitance formed between the gate word line and the common source line is solved. According to the invention, the bonding pad is doubled in the preparation of the device structure.

Description

technical field [0001] The invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a semiconductor structure and a preparation method thereof. Background technique [0002] With the development of planar flash memory, the production process of semiconductors has made great progress. However, in recent years, the development of planar flash memory has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered in planar flash memory and to seek lower production costs per unit storage unit, various three-dimensional (3D) flash memory structures have emerged, for example, 3D NOR (3D or not) Flash memory and 3D NAND (3D NAND) flash memory. However, in the existing three-dimensional memory structure, there is often the problem that the core area of ​​the device occupies a large area, and the leakage ...

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Problems solved by technology

[0004] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a semiconductor structure and a preparation method thereof, which are used to solve the problem of large area occupied by the core area of ​​the preparation of the device structure and the gap between the gate word line and the common source line in the prior art. There are problems such as leakage and parasitic capacitance between the

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