Software and hardware collaborative caching device for improving execution performance of repetitive program

Abstract

The invention discloses a software and hardware collaborative caching device for improving the execution performance of a repetitive program. The device comprises an initial register which is used foridentifying the initial position of a repetitive program segment, an end register which is used for identifying the end position of the repetitive program segment, a counting register which is used for storing the number of times of execution of the repetitive program, a control logic unit which is used for judging whether the repetitive program segment falls into a specific address space or not,controlling an execution packet cache to start to store and distribute an execution packet, clearing control bits of a start register and an end register and maintaining a counting register, and an execution packet caching unit which is used for storing execution packet information distributed to functional components; and after all the execution packets of the repetitive program segment are cached, the execution packet caching unit directly distributes the execution packets to the functional components, and meanwhile, the instruction fetching pipeline is paused. The device has the advantagesof simple structure, simple principle, wide application range and the like.

Description

technical field [0001] The invention mainly relates to the technical field of digital signal processors, in particular to a software-hardware cooperative cache device for improving the performance of repeated program execution. Background technique [0002] As the core of digital signal processing, digital signal processor (DSP) has been widely used in various fields such as aerospace, aviation, radar, sonar, communication, and household appliances, and has become the heart of electronic systems. The development of high-performance and low-power DSP plays an important role in promoting the technological progress in these fields. DSP can quickly realize the processing of signal acquisition, transformation, filtering, evaluation, enhancement, compression, identification, etc., so as to obtain the signal form that meets people's needs. [0003] The instruction characteristic of the DSP of the VLIW architecture is that the fixed-length instruction field is encapsulated into an ...

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Problems solved by technology

[0006] However, there are the following problems in the prior art. Repeatedly executed program segments still need to be re-accessed and decoded, which invisibly increases the impact of memory access delay on program execution efficiency, and also increases the power of program execution. consumption

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