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68 results about "Pipeline (software)" patented technology

In software engineering, a pipeline consists of a chain of processing elements (processes, threads, coroutines, functions, etc.), arranged so that the output of each element is the input of the next; the name is by analogy to a physical pipeline. Usually some amount of buffering is provided between consecutive elements. The information that flows in these pipelines is often a stream of records, bytes, or bits, and the elements of a pipeline may be called filters; this is also called the pipes and filters design pattern. Connecting elements into a pipeline is analogous to function composition.

GPU (graphics processing unit) based software system architecture and UML (unified modeling language) and ADL (architecture description language) combined describing method

The invention discloses a GPU (graphics processing unit) based software system architecture and a UML (unified modeling language) and ADL (architecture description language) combined describing method and belongs to the technical field of software system architectures. The GPU based software system architecture is characterized in that a pipeline and filter mode is applied to modeling, filters include a data stream preprocessing filter, a data stream relief filter, a CPU (central processing unit) loading engine filter, a GPU loading engine filter, a data stream processing filter and a visual filter, original data streams sequentially pass the data stream preprocessing filter, the data stream relief filter, the CPU loading engine filter, the GPU loading engine filter and the data stream processing filter through a pipeline, the data stream processing filter transmits data results to the GPU loading engine filter and the CPU loading engine filter in succession, and the CPU loading engine inputs the data results into the visual filter. UML and ADL are used together, advantages of the UML and the ADL are combined, and the GPU based software system architecture is better established.
Owner:LANGCHAO ELECTRONIC INFORMATION IND CO LTD

Data conversion method based on pipeline three-dimensional model

The invention discloses a data conversion method based on a pipeline three-dimensional model, the combination of SPOOLGEN and multiple software becomes a mainstream working mode at present, but the combination of SPOOLGEN and E3D has the defects that ISO drawings output by SPOOLGEN are inconsistent, the workload is increased for designers to check drawers, the design and construction efficiency isreduced, and the design cost is increased. According to the method, two-dimensional projection is carried out on a pipeline three-dimensional model in E3D software, Excel tables are used for countinginformation of all elements in two-dimensional projection, three-dimensional models of all the elements are established through SolidWorks according to table data, the three-dimensional models of allthe elements are modified, the pipeline three-dimensional model and the elbow three-dimensional model established by SolidWorks are enabled to be consistent with the corresponding pipeline three-dimensional model and elbow three-dimensional model in the SPOOLGEN, the splicing of each three-dimensional model element is completed at the SPOOLGEN, the corresponding valve model is replaced at a specified position, finally a standard ISO graph is output in the SPOOLGEN, and therefore the three-dimensional model in the E3D software obtains a SPOOLGEN standard ISO graph format.
Owner:BOMESC OFFSHORE ENG CO LTD

Continuous integration method for embedded high-safety software

InactiveCN112527380AStrengthen correctness managementVersion controlSoftware testing/debuggingThird partyContinuous integration
The invention relates to a continuous integration method for embedded high-safety software, which is characterized in that the design of a continuous integration assembly line considering the development efficiency and safety of the embedded software comprises a development assembly line and a test assembly line, the development assembly line is executed by developers and comprises environment detection, code construction and code static analysis, and the test assembly line comprises a test assembly line and a test assembly line. The code self-test and result feedback assembly line is executedby a third-party tester and comprises environment detection, code three-party test and result feedback, and a manual link of code review is included between the development assembly line and the testassembly line. Through reasonable continuous integration pipeline design, high efficiency and safety of embedded software research and development are considered, a code static analysis link is introduced before test intervention, so that the problem of tool exposure is solved as soon as possible, and safety is reflected in strengthening correctness management of a research and development environment; and omnibearing code quality assurance measures are taken.
Owner:CHENGDU AIRCRAFT DESIGN INST OF AVIATION IND CORP OF CHINA

Low-power-consumption register allocation compiling optimization method

The invention discloses a low-power-consumption register allocation compiling optimization method. The method comprises the following steps: S1, analyzing a hotspot function and a cycle segment of a program; s2, counting the execution frequency of the dependency statement in the hotspot code segment; s3, registering a life cycle of a temporary variable in the statement with the dependency relationship; s4, closing instruction scheduling optimization related to the performance of the dependency statement to prevent instruction scheduling performed due to consideration of pipeline performance; s5, performing life cycle analysis in the basic block on the temporary variable of each dependency relationship; s6, carrying out cross-basic-block life cycle analysis on the temporary variable of eachdependency relationship; s7, traversing all the basic blocks, and tracking definition and use points (defineuse) of the temporary variables marked as low-power-consumption optimization; and S8, performing Wset instruction loop extraction optimization. According to the invention, the system operation power consumption is optimized to a certain extent, the software and hardware development cost islow, the method for reducing the power consumption is simple and direct, and the low-power-consumption potential of the register is mined to the maximum extent on the premise of considering the performance.
Owner:JIANGNAN INST OF COMPUTING TECH
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