Low-power-consumption register allocation compiling optimization method

A register allocation and optimization method technology, applied in the computer field, can solve problems such as unsatisfactory energy consumption, and achieve the effects of tapping low power consumption potential, low development cost, and optimizing operating power consumption

Active Publication Date: 2021-03-05
JIANGNAN INST OF COMPUTING TECH
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

The traditional compilation and optimization technology has been unable to meet the increasing energy consumption. How to reduce t...

Method used

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  • Low-power-consumption register allocation compiling optimization method

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Embodiment

[0022] Embodiment: a low-power register allocation compilation optimization method, based on the following modules:

[0023] The hardware register file enable setting module is used to control the write-back enable bit of the register file: if the enable is enabled, all specified registers still need to be written back to the register file after bypassing, and if the enable is turned off, all specified registers will be bypassed There is no need to perform a write-back operation afterwards, and the register still retains the old value. The hardware provides the enable control setting for the write-back of the specified register file. The default is to write all the registers back after bypassing. If you need to specify a register for non-write-back operation , open the control setting of the enable bit to the software;

[0024] Software low-power register allocation optimization compiler module, which is used to analyze hot functions that consume large power consumption in the...

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Abstract

The invention discloses a low-power-consumption register allocation compiling optimization method. The method comprises the following steps: S1, analyzing a hotspot function and a cycle segment of a program; s2, counting the execution frequency of the dependency statement in the hotspot code segment; s3, registering a life cycle of a temporary variable in the statement with the dependency relationship; s4, closing instruction scheduling optimization related to the performance of the dependency statement to prevent instruction scheduling performed due to consideration of pipeline performance; s5, performing life cycle analysis in the basic block on the temporary variable of each dependency relationship; s6, carrying out cross-basic-block life cycle analysis on the temporary variable of eachdependency relationship; s7, traversing all the basic blocks, and tracking definition and use points (defineuse) of the temporary variables marked as low-power-consumption optimization; and S8, performing Wset instruction loop extraction optimization. According to the invention, the system operation power consumption is optimized to a certain extent, the software and hardware development cost islow, the method for reducing the power consumption is simple and direct, and the low-power-consumption potential of the register is mined to the maximum extent on the premise of considering the performance.

Description

technical field [0001] The invention relates to a low-power register allocation and compilation optimization method, which belongs to the technical field of computers. Background technique [0002] With the continuous development of hardware technology and architecture, the speed of processors is getting faster and higher, and the degree of on-chip integration is getting higher and higher. While bringing higher processing performance, it also causes huge energy consumption. The development trend of high-performance processors has gradually transitioned from high performance to high performance, that is, high performance and energy consumption ratio. Studies have shown that during the operation of the processor, the power consumption of the register file accounts for 15% to 20% of the total power consumption, and a considerable part of the operation value is passed in the pipeline through the bypass, that is, the instruction obtains the source data from the bypass, The value...

Claims

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Application Information

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IPC IPC(8): G06F8/41
CPCG06F8/41G06F8/441G06F8/4432Y02D10/00
Inventor 朱琪吴伟沈莉王飞肖谦周文浩钱宏武文浩
Owner JIANGNAN INST OF COMPUTING TECH
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