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Fabrication method of semiconductor structure

A manufacturing method, semiconductor technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, semiconductor/solid-state device components, etc., can solve problems such as reducing frequency range, affecting signal transmission speed, resistance and capacitance delay, etc. Electrical constant, improved resistance and capacitance delay phenomenon, low cost effect

Active Publication Date: 2021-01-29
南京晶驱集成电路有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] The purpose of the present invention is to provide a manufacturing method of a semiconductor structure to solve the problem of resistance and capacitance delay of the interconnection structure, affecting signal transmission speed, and reducing the use range of frequencies

Method used

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  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure
  • Fabrication method of semiconductor structure

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Embodiment Construction

[0028] A method for manufacturing a semiconductor structure proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that all the drawings are in a very simplified form and use imprecise scales, and are only used to facilitate and clearly assist the purpose of illustrating the embodiments of the present invention. In addition, the structures shown in the drawings are often a part of the actual structure. In particular, each drawing needs to display different emphases, and sometimes uses different scales.

[0029] An embodiment of the present invention provides a method for manufacturing a semiconductor structure, referring to figure 1 , the method includes the steps of:

[0030] Step S10, providing a substrate;

[0031] Step S20, forming at least one layer of interconnection layers on the substrate, each of the interconnection layers includes a conductive layer and an...

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Abstract

The invention provides a manufacturing method of a semiconductor structure. The manufacturing method comprises the following steps: providing a substrate; and forming at least one interconnection layer on the substrate, wherein each interconnection layer comprises a conductive layer and an interlayer dielectric layer, a conductive layer opening is formed in the conductive layer, the interlayer dielectric layer fills the conductive layer opening, and in at least one interconnection layer, the width of the top of the conductive layer opening is smaller than the width of the bottom of the conductive layer opening, and air bubbles are formed in the interlayer dielectric layer filled in the conductive layer opening. Because air has a low dielectric constant, the dielectric constant can be reduced by adding air bubbles into the interlayer dielectric layer, and the resistance-capacitance delay phenomenon is improved. In addition, a photomask does not need to be added, the process is simple, and cost is low.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] With the development of semiconductor technology, the integration level of VLSI chips has reached hundreds of millions or even billions of devices, and multilayer metal interconnection technology is widely used. The fabrication method of the metal interconnect layer generally includes: first, depositing an inter-layer dielectric layer (Inter-layer dielectric, ILD); then, forming trenches (trench) and via holes in the inter-layer dielectric layer by photolithography and etching processes (via); then, metal is deposited in the aforementioned trenches and through holes, and the deposited metal forms a metal interconnection structure. Because copper has good electrical conductivity and filling properties, copper is usually selected as the material of the metal interconnection line. [0003] H...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/768H01L23/528H01L23/535
CPCH01L21/76804H01L21/76816H01L21/76877H01L23/5283H01L23/535
Inventor 祝进专李庆民林滔天王梦慧
Owner 南京晶驱集成电路有限公司