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Method for real-time full duplex reliable communication between MCU and multiple FPGAs by using SPIs

A full-duplex, reliable technology, applied in the direction of instrumentation, electrical digital data processing, etc., can solve the problem that the communication speed between MCU and FPGA has not been effectively improved, real-time and reliable transmission of variable-length data cannot be performed reliably, full-duplex and bus are not fully utilized, etc. problem, to achieve the effect of improving reliability

Inactive Publication Date: 2020-11-20
西安爱生无人机技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0010] The purpose of the present invention is to solve the problem of using SPI between the MCU and multiple FPGAs in the prior art, mainly for reading and writing of registers and continuous reading of data, and does not make full use of its full-duplex and bus characteristics, which cannot be real-time and reliable. To solve the problem of transmitting variable-length data, and the communication speed between MCU and FPGA has not been effectively improved, a method for real-time full-duplex reliable communication between MCU and multiple FPGAs using SPI is provided

Method used

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  • Method for real-time full duplex reliable communication between MCU and multiple FPGAs by using SPIs
  • Method for real-time full duplex reliable communication between MCU and multiple FPGAs by using SPIs
  • Method for real-time full duplex reliable communication between MCU and multiple FPGAs by using SPIs

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Embodiment Construction

[0045] The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0046] A kind of MCU provided by the present invention uses SPI to carry out the method for real-time full-duplex reliable communication with a plurality of FPGAs, MCU is connected with a plurality of FPGAs, such as figure 1 As shown, the MCU is the host, the FPGA is the slave, and the MCU communicates with multiple FPGAs using SPI.

[0047] The clock phase (CPHA) and clock polarity (CPOL) of SPI can be 0 or 1 respectively, and the corresponding four combinations constitute the four modes of SPI, which are:

[0048] Mode 0: CPOL=0, CPHA=0;

[0049] Mode 1: CPOL=0, CPHA=1;

[0050] Mode 2: CPOL=1, CPHA=0;

[0051] Mode 3: CPOL=1, CPHA=1.

[0052] Clock polarity CPOL, that is, the level of the clock signal SCLK when the SPI is idle (1: high level when idle; 0: low level when idle);

[0053] Clock phase CPHA, that is, on which edge of SCLK ...

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Abstract

The invention discloses a method for real-time full duplex reliable communication between an MCU and multiple FPGAs by using SPIs, and aims to solve the problems that in the prior art, the characteristics of SPI full duplex and a bus are not fully utilized, uncertain-length data cannot be reliably transmitted in real time, and the communication speed of the MCU and the FPGAs is not effectively increased. According to the invention, the MCU terminal is used as a host to continuously and cyclically send the sub-data to the plurality of FPGA terminals through the SPI, and the plurality of FPGA terminals are used as slaves to continuously and cyclically send the sub-data to the MCU terminal through the SPI after receiving the enable signal of the host. After receiving the sub-data, the two parties judge data properties according to the first byte, directly discard the sub-data if the sub-data are invalid, and resend the sub-data if there is a resending application, it is judged whether thecheck bit is correct or not if the sub-data are valid, resending is applied for if the check bit is incorrect, the frame data length is calculated according to the second to third bytes if the checkbit is correct, and complete frame data is formed.

Description

technical field [0001] The invention relates to a method for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPI. Background technique [0002] In the field of communication, it is a common scenario to use FPGA to process data with chips of other architectures, and SPI is the abbreviation of Serial Peripheral Interface (Serial Peripheral Interface), which is a high-speed, full-duplex, synchronous communication bus. The number of pins is small, the data transmission rate is high, and the logic is relatively simple compared with the ultra-high-speed interface. Therefore, it can be used for full-duplex communication between MCU and FPGA. [0003] At present, the use of SPI between MCU and multiple FPGAs is mainly for reading and writing of registers and continuous reading of data. It does not make full use of its full-duplex and bus characteristics, and cannot reliably transmit variable-length data in real time. Moreover, the MCU and FPGA T...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42
CPCG06F13/4282
Inventor 袁钟达樊立明杨翠翠杨健王剑飞李晨曦李泽辰李海飞李龙洲黄迟张立雄王磊刘洋
Owner 西安爱生无人机技术有限公司
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