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Parallel logic operation method based on multi-bit nonvolatile memory and full adder

A non-volatile memory and non-volatile storage technology, applied in the field of full adder, can solve the problems of time and energy consumption, limited bandwidth, complicated operation steps, etc., to alleviate the problems of extra delay and energy consumption, and achieve high-efficiency parallelism The effect of calculation ability and efficient logical operation ability

Active Publication Date: 2020-11-27
UNIV OF SCI & TECH OF CHINA
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Problems solved by technology

However, the data of these traditional digital operation units is volatile, and the data needs to be obtained by accessing storage units other than the operation unit, which leads to limited bandwidth and time-consuming and energy-consuming calculations.
Recently, people have developed a method of in-memory logic operation based on non-volatile memory, but Boolean logic is still implemented based on 1-bit memory, so a large number of memory devices and complicated operation steps are required

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  • Parallel logic operation method based on multi-bit nonvolatile memory and full adder
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Embodiment Construction

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0043] As mentioned in the background, in modern computers, the logical operation unit is composed of CMOS transistors, and its Boolean logic operations are all performed by level logic, that is, binary 0 and 1 logic are represented by high and low levels respectively. However, the traditional digital operation unit is accompanied by data volatility, and the data acquisition and result storage need to access the storage unit other than the operation unit, which...

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Abstract

The invention provides a parallel logic operation method based on a multi-bit nonvolatile memory and a full adder, the input is different levels and device nonvolatile storage states, and the output is the device nonvolatile storage state obtained based on the logic operation rule. The parallel logic operation method is suitable for any nonvolatile memory which has a multi-bit storage state and can be converted between different storage states. Based on the method, 16 complete Boolean logic functions can be completed by using one memory under two-step operation, and multiple sets of logic functions can be realized in parallel in the operation process. The N-bit full adder designed on the basis only needs three storage devices to carry out (3N+2)-step operation, so that the addition operation can be realized, and the N-bit full adder has efficient operational capability.

Description

technical field [0001] The invention relates to the technical field of integration of storage and calculation, and more specifically, relates to a method for realizing parallel logic operation based on a multi-bit nonvolatile memory, and a full adder designed based on the method. Background technique [0002] In the era of big data, low energy consumption, high-efficiency storage and processing of massive data is one of the keys to promoting the development of artificial intelligence, Internet of Things and other technologies in the future. However, modern computers adopt an architecture in which data storage and processing are separated, requiring data to be transferred between different memories and processors, which brings additional delay and energy consumption, which is called the "von Neumann bottleneck". In-memory computing technology, that is, the technology of realizing data calculation in memory, is considered to be an effective way to break through this bottleneck...

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Application Information

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IPC IPC(8): G11C11/56G06F7/501
CPCG11C11/5607G11C11/5657G11C11/5678G11C11/5614G06F7/501Y02D10/00
Inventor 马超陶临风罗振金西殷月伟李晓光
Owner UNIV OF SCI & TECH OF CHINA
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