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Decoding circuit and chip

A decoding circuit and level technology, applied in circuit devices, battery circuit devices, current collectors, etc., can solve the problems of poor error correction and communication distance communication signal adaptability, heavy MCU calculation burden, etc., so as to reduce the calculation burden and solve the problem of calculation The effect of the heavy load and the elimination of the influence of the communication signal

Active Publication Date: 2020-12-04
SHANGHAI XINLONG SEMICON TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The purpose of the present invention is to provide a decoding circuit and chip to solve the problems of the existing communication signal decoding scheme of the HBS protocol, which have a heavy computational burden on the MCU, contradictions between error correction and communication distance, and adaptation to communication signals of different clock cycles. sex problem

Method used

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  • Decoding circuit and chip
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  • Decoding circuit and chip

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Experimental program
Comparison scheme
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Embodiment 1

[0040] Please refer to Figure 1 to Figure 2 ,in, figure 1 is a schematic structural diagram of a decoding circuit according to Embodiment 1 of the present invention; figure 2 It is a schematic diagram of the waveform of the decoding circuit of Embodiment 1 of the present invention under a signal.

[0041] Such as figure 1 As shown, this embodiment provides a decoding circuit, including a charging and discharging unit 100, a capacitor 200, and a conversion unit 300 connected in sequence, wherein,

[0042] The charging and discharging unit 100 is configured to charge the capacitor 200 when receiving a first level, and discharge the capacitor 200 when receiving a second level; wherein, charging the capacitor 200 with any The ratio of the total duration consumed by the electricity to the total duration consumed by the capacitor 200 to release the same electricity is a preset value;

[0043] The conversion unit is configured to output a third level when the voltage of the cap...

Embodiment 2

[0064] Please refer to Figure 3 to Figure 5c ,in image 3 is a schematic circuit diagram of a decoding circuit according to Embodiment 2 of the present invention; Figure 4 It is a schematic diagram of the output waveform of the decoding circuit in Embodiment 2 of the present invention under the communication signal without interference; Figure 5a It is a schematic diagram of the output waveform of a software decoding scheme under a communication signal with interference; Figure 5b It is a schematic diagram of the output waveform of the decoding circuit in Embodiment 2 of the present invention under the interference communication signal; Figure 5c yes Figure 5b The partially enlarged schematic diagram of part A in the middle.

[0065] As shown in the figure, this embodiment provides a decoding circuit, the decoding circuit includes a charging and discharging unit 100, a capacitor 200, a conversion unit 300, a first reference unit 400 and a second reference unit 500, t...

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Abstract

The invention provides a decoding circuit and a chip. The decoding circuit comprises a charging and discharging unit, a capacitor and a conversion unit which are connected in sequence. The charging and discharging unit is configured to charge and discharge the capacitor, wherein the ratio of the total duration consumed by charging the capacitor with any amount of electricity to the total durationconsumed by releasing the same amount of electricity from the capacitor is a preset value. The conversion unit is configured to output a third level when the voltage of the capacitor exceeds a presetvoltage, otherwise, output a fourth level. Through the configuration, the calculation burden of an MCU is reduced, the influence of noise on communication signals is eliminated, and the effective communication distance of the HBS protocol is increased; and communication signals of different clock periods are self-adapted. The problems that in the prior art, an MCU is large in calculation burden, contradictions exist between error correction and the communication distance, and the adaptability to communication signals of different clock periods is poor are solved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit chips, in particular to a decoding circuit and a chip. Background technique [0002] In the fields of air conditioning, security, smart home, etc., the communication between the host and the slave mostly adopts the HBS (HomeBUS, referred to as HBS) communication protocol, which has the advantage of supporting twisted pair for communication and power supply, that is Twisted pair wires are used not only for communication, but also for supplying power to downstream equipment; when connecting devices, twisted pair wires do not need to distinguish polarity, and there is no polarity connection; it brings great convenience to on-site construction and installation. In the prior art, using the HBS protocol for communication has the following three problems: [0003] First, the encoding rule of the HBS protocol is to encode the high-level signal "1" as "11", and the low-level signal "0" as "01"....

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04B14/02H02J7/34
CPCH04B14/023H02J7/345H04B14/026H04B3/54H04B2203/5416H04B2203/5408H04L12/40032H03M7/007H03M7/60
Inventor 李瑞平池伟刘彬王建虎
Owner SHANGHAI XINLONG SEMICON TECH CO LTD