DDR3 read-write transmission method and device

Abstract

The invention relates to a DDR3 read-write transmission method. The DDR3 read-write transmission method comprises the process of writing data into a DDR3 storage module; wherein the process of writingthe data into the DDR3 storage module comprises the following steps: outputting a full state to the DDR3 writing module by an RAM configured in each DMA writing data channel; wherein the full state is used for representing the maximum data volume which can be cached by the RAM; and the DDR3 writing module receives the full state output by each path of RAM, and writes data into the DDR3 storage module according to the current mark of the full state output by each path of RAM. According to the method, when data writing operation is carried out, one RAM is configured in each DDR3 data writing channel, and each RAM is provided with a full-state mark, so that during writing operation, data cached in the RAM can be uniformly written into the DDR3 storage module in a burst mode, and the data writing speed is effectively increased.

Description

technical field [0001] The present application relates to the technical field of memory, in particular to a DDR3 read-write transmission method and device. Background technique [0002] DDR3 SDRAM, as the third generation of double-rate synchronous dynamic random access memory, has the advantages of large capacity, high speed and low power consumption, and has been widely used in computer, electronic communication and other fields. However, there are a large number of read-write conflicts in the existing DDR3 read and write, and the simultaneous read and write control of DDR3 is relatively weak, which makes the existing DDR3 have a low frequency of read and write transmission and a slow operating speed. This makes DDR3 cannot be flexibly applied to product design. Contents of the invention [0003] In view of this, the present application proposes a DDR3 read / write transmission method, which can effectively increase the DDR3 data read / write rate, so that DDR3 can be flexi...

AI Technical Summary

Problems solved by technology

However, there are a large number of read-write conflicts in the existing DDR3 read and write, and the simultaneous read and write control of DDR3 is relatively weak, which makes the current DDR3 have a low frequency of read and write transmission and a slow operating speed. Make DDR3 can not be flexibly applied to product design

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