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DMA controller and data transmission method thereof

A DMA controller and data technology, applied in the direction of electrical digital data processing, instruments, etc., can solve problems such as data loss, data and Cache data inconsistency, reduce DMA transmission performance, etc., and achieve the effect of improving performance

Pending Publication Date: 2020-12-22
SUZHOU CENTEC COMM CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] Because on the CPU side, there is generally a cache cache between the main memory and the CPU processor, that is to say, the memory seen by the process address space in the CPU is the data in the cache, not the data in the main memory, such as figure 1 As shown, when the DMA transfers data to the main memory, there will be a certain time difference between the data in the main memory and the data in the Cache, and there may be inconsistencies between the data in the main memory and the data in the Cache, which will cause the CPU to follow the process after receiving an interrupt. In order to solve the problem of data consistency between the Cache and the main memory, the traditional method will directly close the Cache after receiving an interrupt, skip the Cache and directly read the data in the main memory. In actual DMA applications, especially when sending and receiving messages and reading table entries in the network processor, these applications are constantly sending data. If the CPU uses DMA data every time it reads The method of "closing the Cache directly after receiving the interrupt, skipping the Cache and directly reading the main memory data" will greatly reduce the DMA transfer performance

Method used

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  • DMA controller and data transmission method thereof
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  • DMA controller and data transmission method thereof

Examples

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Embodiment 1

[0030] figure 1 It is a schematic diagram of the structure of the data transmission system between the DMA controller and the CPU. Such as figure 1 As shown, the present invention provides a direct memory access DMA controller, and the DMA controller includes:

[0031] Detecting the descriptor state unit, for when the DMA controller transmits data to the CPU or receives data from the CPU, detects the value of the state indicator bit Done of the descriptor corresponding to the data, and the DMA controller is based on the detection result to The data is processed; wherein, the value of the status indication bit Done is 0 or 1, Done=1 indicates that the descriptor is valid, and Done=0 indicates that the descriptor is idle.

[0032]The DMA controller also includes a read-write main memory data unit. When the DMA controller transmits data to the CPU, the DMA controller judges whether there is a descriptor with a status indication bit Done=0, if not, Then terminate the data trans...

Embodiment 2

[0043] Figure 4 It is a flow chart of the method when the DMA controller performs data transmission. exist Figure 4 In, when the DMA controller transmits data to the CPU or receives data from the CPU, the detection descriptor state unit in the DMA controller detects the value of the state indication bit Done of the descriptor corresponding to the data, and the DMA controller The data is processed based on the detection result; wherein, the value of the status indication bit Done is 0 or 1, Done=1 indicates that the descriptor is valid, and Done=0 indicates that the descriptor is idle.

[0044] Preferably, when the DMA controller transmits data to the CPU, the DMA controller judges whether there is a descriptor with a status indicating bit Done=0, if not, then terminates the data transmission; if it exists, then the The read-write main memory data unit in the DMA controller writes data to the data address of the main memory corresponding to the descriptor through the contro...

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Abstract

The present invention relates to a DMA controller and a data transmission method thereof. The DMA controller comprises a descriptor state detection unit for detecting a value of a state indication bitDone of a descriptor corresponding to data when the DMA controller transmits the data to a CPU or receives the data from the CPU, and the DMA controller processing the data based on the detection result. By adding the descriptor state detection unit in the DMA controller, when data is transmitted between the DMA controller and the CPU, the operation is carried out according to the state indication bit Done of the descriptor, and whether a main memory and the Cache are synchronous or not does not need to be concerned, so that data loss caused by the fact that data transmitted by the DMA controller is not obtained from an address space of a process after the CPU receives interruption is avoided, and the data transmission performance of the CPU and the DMA controller can be greatly improved.

Description

technical field [0001] The invention relates to the technical field of network equipment, in particular to a DMA controller and a data transmission method thereof. Background technique [0002] In general, DMA transfers copy data from one address space to another. When the CPU initiates the transfer, the transfer itself is executed and completed by the DMA controller. A typical example is moving a block of external memory to a faster memory area inside the chip. Instead of stalling processor work, operations like this can be rescheduled to handle other work. DMA transfers are important for high-performance embedded system algorithms and networks. [0003] When implementing DMA transmission, the DMA controller is directly in charge of the bus, so there is a problem of bus control right transfer. That is, before the DMA transfer, the CPU should hand over the control of the bus to the DMA controller, and after the DMA transfer is completed, the DMA controller should immedia...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/32
CPCG06F13/32
Inventor 何志川徐海青王义东
Owner SUZHOU CENTEC COMM CO LTD