Microprocessor

Abstract

The invention provides a microprocessor in which a branch predictor and an instruction cache are decoupled by an instruction fetching target queue, and the instruction fetching target queue provides an instruction fetching failure solution. In response to an instruction fetch failure of a target instruction fetch address, the instruction fetches the target instruction fetch address from the instruction fetch target queue again and restores an instruction fetch address. Therefore, the branch predictor can greatly lead the instruction cache to operate.

Description

technical field [0001] This application is about instruction fetching for microprocessors. Background technique [0002] In computer architecture, a branch predictor (branch predictor) is generally implemented with digital circuits to predict branch instructions (such as "if-then-else" conditional branch instructions, "call" call instructions, "return" return instructions, and "jump "Unconditional branch instruction) jump. The branch predictor effectively accelerates the instruction fetching of the microprocessor, and significantly improves the performance of the pipelined microprocessor. [0003] However, instruction fetching may fail, and how to improve this is an important issue in this technical field. Contents of the invention [0004] In the present application, an instruction fetch target queue decoupling a branch predictor and an instruction cache is used to handle instruction fetch failure events. [0005] A microprocessor implemented according to an embodiment...

AI Technical Summary

Problems solved by technology

[0003] However, instruction fetching may fail, how to improve this is an important topic in this technical field

Images