Novel distributed array and contact architecture for 4-stack 3D X-point memory

A memory and contact technology, applied in the field of three-dimensional electronic memory, can solve problems such as high cost

Active Publication Date: 2021-01-01
YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication tech...

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  • Novel distributed array and contact architecture for 4-stack 3D X-point memory
  • Novel distributed array and contact architecture for 4-stack 3D X-point memory
  • Novel distributed array and contact architecture for 4-stack 3D X-point memory

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Embodiment Construction

[0015] The technology is applied in the field of three-dimensional memory. exist figure 1 A general example of a three-dimensional (3D) memory is shown in . in particular, figure 1 is a perspective view of a portion of a three-dimensional intersection memory. The memory includes a first layer storage unit 5 and a second layer storage unit 10 . Between the first layer memory cells 5 and the second layer memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. In the depth (Z) direction, a plurality of first bit lines 20 extending along the vertical (Y) direction are above the first layer of memory cells 5, and a plurality of first bit lines 20 extending along the Y direction are below the second layer of memory cells 10. A second bit line 25.

[0016] further as figure 1 As shown in , the sequential structure of bit line, memory cell, word line, memory cell can be repeated along the Z direction to form a stacked configuration. exist fi...

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Abstract

A three-dimensional memory includes a bottom cell layer of a memory cell, a top cell layer of the memory cell, and at least one intermediate cell layer of the memory cell. The bottom cell layer is coupled to the bottom cell bit line, the bottom cell bit line decoder, the bottom cell word line, and the bottom cell word line decoder. The intermediate cell layer is coupled to an intermediate cell bitline, an intermediate cell bit line decoder, a bottom or intermediate cell word line, and a bottom or intermediate cell word line decoder. The top cell layer is coupled to the top cell bit line, thebottom cell bit line decoder, the intermediate cell word line, and the intermediate cell word line decoder. A bit line decoder may be arranged in a sub-portion offset in a vertical direction. A word line decoder may be arranged in a sub-portion offset in a horizontal direction.

Description

technical field [0001] In general, the present disclosure relates to three-dimensional electronic memory, and in particular, the present disclosure relates to increasing the density of memory cells in three-dimensional cross-point (X-point) memory. Background technique [0002] Planar memory cells are shrunk to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. Therefore, the storage density of planar memory cells approaches the upper limit. There remains a need for three-dimensional (3D) memory architectures that can address the density limitations in planar memory cells. Contents of the invention [0003] The three-dimensional memory and methods disclosed herein solve the problems of the state of the art and provide additional benefits. According to one aspec...

Claims

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Application Information

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IPC IPC(8): G11C7/18G11C8/10G11C8/14H01L45/00
CPCG11C7/18G11C8/10G11C8/14H10N70/801H10N70/20H10N70/826
Inventor 刘峻
Owner YANGTZE ADVANCED MEMORY INDUSTRIAL INNOVATION CENTER CO LTD
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