Connection network of integrated circuit, integrated circuit, chip and electronic equipment

Abstract

The embodiment of the invention discloses a connection network of an integrated circuit, the integrated circuit, a chip and electronic equipment, and belongs to the technical field of microelectronics. The wiring network provided by the invention comprises a metal layer, a middle partition layer, a rewiring layer, a power supply salient point and a grounding salient point which are stacked in thevertical direction, and the included angle between the extending direction of a wire in the metal layer and the extending direction of a wire in the rewiring layer is smaller than 90 degrees and larger than 0 degree. Since the lead in the redistribution layer and the lead in the metal layer are not equal to 90 degrees, i.e., the lead in the redistribution layer can be used as leads in the horizontal direction and the vertical direction between the conduction logic element and the salient point, and the resistance of the lead in the redistribution layer is smaller than that of the lead in the metal layer with the same length, the wiring resistance of the integrated circuit can be reduced through the wiring network, and the voltage drop on the integrated circuit is reduced, so the time delayof the integrated circuit is reduced, and the performance of the integrated circuit is improved.

Description

technical field [0001] The embodiments of the present application relate to the technical field of microelectronics, and in particular, relate to a wiring network of an integrated circuit, an integrated circuit, a chip, and an electronic device. Background technique [0002] With the development of the modern electronics industry, the demand for chips is also increasing. In chip manufacturing, high wire resistance causes a voltage drop in the chip, which slows down the switching speed of the logic gate of the chip and affects the performance of the chip. [0003] In the related art, a chip manufacturer will set a bump (bump) plate when processing a chip. The spacing between adjacent bumps will be set according to the minimum allowable spacing, so that the logic elements in the chip can be connected to the circuit through the shortest possible wiring distance. Contents of the invention [0004] The embodiments of the present application provide a wiring network of an inte...

AI Technical Summary

Problems solved by technology

In chip manufacturing, high wire resistance causes a voltage drop in the chip, which slows down the switching speed of the chip logic gate and affects the performance of the chip.

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