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EFM signal frame period detecting circuit, and system for controlling frequency of bit synchronizing clock signal used for reproducing the EFM signal

A technology of frame period and signal frame, applied in the circuit field of bit synchronous clock signal

Inactive Publication Date: 2003-10-08
NEC ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, for this purpose, since the duration for detecting the frame synchronization signal is set to several times the predetermined frame period, it will take a long time to finish reproducing the EFM signal.

Method used

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  • EFM signal frame period detecting circuit, and system for controlling frequency of bit synchronizing clock signal used for reproducing the EFM signal
  • EFM signal frame period detecting circuit, and system for controlling frequency of bit synchronizing clock signal used for reproducing the EFM signal
  • EFM signal frame period detecting circuit, and system for controlling frequency of bit synchronizing clock signal used for reproducing the EFM signal

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Embodiment Construction

[0017] Embodiments of a system for controlling the frequency of a bit-synchronized clock signal for reproducing an EFM signal according to the present invention will now be described with reference to the accompanying drawings.

[0018] refer to figure 2 , according to the first embodiment of the system for controlling the frequency of the bit synchronous clock signal used for replaying EFM signals comprising an EFM signal frame period detection device 1, which receives an EFM signal 10 to generate a frame period signal 11 A bit synchronous clock signal generator 2 for generating a bit synchronous clock signal 21; A frequency control device 3, for receiving EFM signal 10, the frame period signal 11 output from EFM signal frame period detection device 1, and in The bit synchronous clock signal 21 produced in the bit synchronous clock signal generator 2, and output a frequency rise-fall control signal 31 to the bit synchronous clock signal generator 2; And one receives the EFM s...

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Abstract

A system for controlling the frequency of a bit synchronizing clock signal used for reproducing an EFM signal, comprises an EFM signal frame period detecting circuit for frequency-dividing an EFM signal by 117 to output a 1 / 117 frequency-divided signal as a frame period signal. A control unit counts the level transition interval of the EFM signal by the bit synchronizing clock signal, selects a maximum count value in a detecting duration defined by each frame period signal, and compares the maximum count value with a predetermined value corresponding to the bit length of a frame synchronizing signal included in the EFM signal.

Description

technical field [0001] The invention relates to a circuit for obtaining a bit-synchronous clock signal for playback of an EFM (Eight to Fourteen Modulation) signal. More particularly, the present invention relates to an EFM signal frame period detection circuit and a system for controlling the frequency of a bit-synchronized clock signal used to reproduce the EFM signal. Background technique [0002] In international standards such as IEC908 and Japanese domestic standards such as JIS8605 (1993), EFM signals are described as a standard signal modulation system for recording digital signals on optical discs. In the EFM system, a source signal is divided into multiple 8-bit units, and each 8-bit unit is called a "symbol". A symbol (made up of 8 bits) is converted into a signal made up of 14 bits, as shown in Figure 1. At this time, each 14-bit symbol is called a "channel bit". A signal consisting of 14 channel bits is constructed in such a way that the minimum interval betw...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11B20/14G11B27/30H03M5/14H04L7/02H04L7/08H04L25/40H04L25/49
CPCG11B20/1403H04L7/02G11B27/3027G11B20/1426G11B2020/1461
Inventor 千叶敏成野川浩道
Owner NEC ELECTRONICS CORP