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Unified programmable computational memory and configuration network

A memory and network technology used in the field of programmable devices

Pending Publication Date: 2021-02-23
XILINX INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

In some cases, the architecture of the programmable logic region may present challenges in communicating signals with the programmable logic region

Method used

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  • Unified programmable computational memory and configuration network
  • Unified programmable computational memory and configuration network
  • Unified programmable computational memory and configuration network

Examples

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Embodiment Construction

[0030] Examples described herein relate generally to programmable devices with a unified programmable computing memory and configuration network. Configuration data for configuring a Programmable Computing Memory (PCM) block may be transmitted via the network, and transaction data, eg, generated by the PCM block during operation of a functional mode based on the configuration data, may also be transmitted via the network. Accordingly, the network may be operable to transmit configuration data and transaction data.

[0031] Some examples may include or be a programmable device having one or more PCM dies, each PCM die having a region or array comprising PCM blocks, each of which may implement block memory and programmable logic. Programmable devices may also include programmable logic (PL) dies. PCM dies may be fabricated at processing nodes that are smaller than that of PL dies. Each PCM die can be viewed as a PCM comprising resources that can be dynamically allocated betwee...

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Abstract

The embodiment of the disclosure relates to a unified programmable computational memory and a configuration network. Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal ofa group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.

Description

technical field [0001] Examples of the present disclosure relate generally to programmable devices and methods of operating such programmable devices, and in particular to programmable devices having a unified programmable computing memory and configuration network and methods for operating such programmable devices. Background technique [0002] Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs), are typically integrated circuits (ICs) that include programmable logic. Programmable logic may be in a region of the IC, such as a programmable logic region. The programmable logic region of an IC may also be referred to as a structure within the IC. Programmable logic regions may be programmable to be configured to implement various logic functions, applications or cores. Logic functions and the like can be performed on signals received by the programmable logic region from some circuit outside the programmable logic region, and can generate signa...

Claims

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Application Information

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IPC IPC(8): G06F30/343
CPCG06F30/343G06F7/483G06F7/502H03K19/17724H03K19/1774H03K19/17744H03K19/17756H03K19/1776G06F3/067
Inventor R·C·卡马罗塔
Owner XILINX INC
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