IO PAD automatic layout method with self-checking function

Abstract

The invention discloses an IO PAD automatic layout method with a self-checking function, and the method is characterized in that the method comprises the steps: 1, reading and writing a filled configuration file; 2, according to the configuration file, generating an IO PAD DEF file and a pin-assignment table file; 3, checking IO PAD layout; if the IO PAD layout does not pass the inspection, executing the step 1 again; and 4, when the IO PAD needs to be rearranged, adjusting IO list information in the configuration file, repeating the above the steps, and generating a new IO PAD DEF file and anew pin-assignment table file. The method has the beneficial effects that the IO PAD layout can be quickly and efficiently achieved, the integrity and consistency of the IO PAD layout and whether SSO,ESD and Latch-up design rules are violated or not are automatically checked, and the efficiency of chip back-end physical design is remarkably improved.

Description

technical field [0001] The invention relates to the field of chip design, in particular to a method for automatic layout of an IO PAD with a self-checking function. Background technique [0002] The traditional way of IO PAD layout is to manually layout in the back-end implementation tool or manually edit the IO PAD file supported by the back-end implementation tool. With the rapid development of the integrated circuit industry, the integration of chips is increasing according to Moore's Law, the scale is getting bigger and bigger, and the functions are becoming more and more complex, resulting in more and more IO PADs on the chip, and the scale reaches Hundreds or thousands, which puts higher requirements on the method of chip IO PAD layout. Developing an automatic process with self-checking function for the IO PAD layout of the system chip will greatly improve the chip back-end physics. Designed for efficiency. [0003] The traditional technology has the following techni...

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Problems solved by technology

[0004] In the process of physical realization of the entire chip, with the continuous improvement or adjustment of the front-end design, the adjustment of the top-level layout of the back-end, or the adjustment of the chip package design, the IO PAD layout needs to be adjusted accordingly. Therefore, the IO PAD layout is a continuous process. In the process of iterative and multiple optimization convergence, the traditional IO PAD layout method has great defects. Every time the IOPAD layout is adjusted, the IO PAD file needs to be re-edited. The workload is huge, repetitive, and tedious, which requires a lot of manpower and time. Moreover, the efficiency is low, errors are prone to occur and it is difficult to check and correct errors in time, which seriously affects the quality of chip physical design and engineering convergence time

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