A level conversion circuit

Abstract

The invention discloses a level conversion circuit, which relates to the technical field of integrated circuits. The level conversion circuit includes a first field effect transistor and a second field effect transistor connected to a power supply voltage, a third field effect transistor, a first high-voltage native transistor and a first low-voltage field effect transistor connected to the first input end, connected to the The fourth FET, the second high-voltage native transistor and the second low-voltage FET at the second input end, the fourth FET, the second high-voltage native transistor and the second low-voltage FET are also connected to the circuit output through an inverter terminal; the first field effect transistor is connected to the third field effect transistor, the fourth field effect transistor and the second high voltage native tube; the second field effect transistor is connected to the third field effect transistor, the fourth field effect transistor and the first high voltage native tube tube; the first high-voltage native tube is grounded through the first low-voltage field effect tube, and the second high-voltage native tube is grounded through the second low-voltage field effect tube. The technical scheme of the present invention realizes the conversion of the wide power supply voltage of the circuit.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, in particular to a level conversion circuit. Background technique [0002] Level shifting circuits are very common in analog circuits and are often used to convert between different levels to boost low voltage signals to high voltage levels. However, with the further reduction of the operating voltage of low-voltage devices, the traditional low-voltage to high-voltage level conversion circuit encounters a bottleneck in a wide power supply range. E.g figure 1 In the traditional structure, the field effect transistors in the circuit are all high voltage tubes. Under normal circumstances, when the input terminals V1 and V2 receive a low-voltage 1.2V clock input, they can output a 3.3V high-voltage clock at the CLK_OUT terminal, and the voltages are all typical values. In other demanding applications, the voltage conversion can exceed ten percent, that is, the maximum level con...

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Problems solved by technology

[0003] However, with the continuous improvement of application requirements, some applications require devices to support low voltage of 0.9V, or even lower than 0.9V, figure 1 The NMOS transistors N1 and N2 in the circuit structure will not be able to conduct

If will figure 1 If the NMOS tube in the circuit structure is replaced by a low-voltage tube, it will face the problem of its withstand voltage that cannot be solved.

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