Integrated Circuit Finely Adjusts the Layout Structure of Resistor Arrays

Abstract

The invention discloses an integrated circuit fine-tuning resistor array layout structure, which includes N resistors, N metal leads, a first resistor port and a second resistor port; the N resistors are arranged in parallel with each other, and the N resistors are respectively resistors R 1 , resistance R 2 , resistance R 3 ,..., resistance R N‑2 , resistance R N‑1 with resistor R N , where the resistor R 1 The resistance value of the resistance is equal to R / N. As the resistance subscript number increases, the resistance value of the corresponding resistance increases by R / N in turn until the resistance R N The resistance value of R is R; N metal leads, N metal leads are parallel to each other, one end of N metal leads and one end of N resistors are interconnected in one-to-one correspondence; the first resistor port and the other end of N metal leads can be selected The second resistor port is interconnected with the other ends of the N resistors in a one-to-one correspondence. The invention can finely adjust the resistance value in a large range.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an integrated circuit fine-tuning resistor array layout structure. Background technique [0002] In the process of integrated circuit design, it is often encountered that some circuits are particularly sensitive to the resistance value, and the uncertainty of the resistance value in the process often has an important impact on the final performance of the circuit. In the layout of integrated circuits, resistors can generally be divided into P well / N well resistors, P+ / N+ resistors, P+ / N+ doped polysilicon resistors, ordinary polysilicon resistors and other types. In the process of ion implantation or material preparation, It is inevitable that some resistors will have large deviations in a certain resistance range, which affects the accurate estimation of some resistor values. In order to avoid the large impact of sensitive resistance value process deviation on the p...

AI Technical Summary

Problems solved by technology

[0003] Traditional integrated circuit resistor layout trimming methods generally only connect multiple resistors in parallel or in series to the circuit. It is difficult to meet the requirements of small footprint, wide resistance value range, and high trimming accuracy at the same time. For different needs, often It is necessary to change its trimming resistor layout structure, leaving less space for resistor trimming

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