Three-wire SPI communication system and method
A communication system, three-wire technology, applied in the field of electrical data processing, can solve problems such as increasing the complexity of the connection, and achieve the effect of simplifying the physical connection
Inactive Publication Date: 2021-03-26
苏州锐联芯半导体有限公司
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Problems solved by technology
If there are many slave devices, the connection lines between the master device and the slave devices will increase as the number of slave devices increases, which greatly increases the complexity of the connection
Method used
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[0042] refer to figure 1 The SPI communication system includes a master device and a slave device, and the master device and the slave device are connected by three SPI communication lines, and these three root lines are respectively CS chip select lines, SCLK clock lines, and SDA data lines; A clock generator MCG is set in the master device MASTER, and the output port of the clock generator is connected to the SCLK clock line pin; the clock generator can be simulated by software, or it can be a hardware clock generator. The CS chip selection signal line is the SPI enable signal line of the slave device. When transmitting data, the master device first pulls down the level on the CS chip selection signal line, so that the corresponding slave device enters the data transmission state. There can be one or more slave devices. When there are multiple slave devices, the CS chip select signal line of each slave device will be connected to the IO port of the master device. The master ...
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The invention relates to a three-wire SPI communication system. The system comprises a master device and a slave device. The master device and the slave device are connected through three SPI communication lines, and the three lines are respectively a CS chip selection line, an SCLK clock line and an SDA data line; a clock generator is arranged in the master device, and an output port of the clockgenerator is connected with an SCLK clock line pin; and the SDA data line transmits data in a time-sharing manner, and transmits data in one of the following two manners: executing master device output and slave device input at the rising edge of the SCLK clock line, and executing master device input and slave device output at the falling edge of the SCLK clock line; or executing master device input and slave device output on the rising edge of the clock signal, and executing slave device input and master device output on the falling edge of the clock signal. According to the scheme, the number of communication lines is reduced to three, so that physical connection between the master device and the slave device is greatly simplified.
Description
technical field [0001] The application belongs to the field of electrical data processing, and in particular relates to a modification of a method for transmitting or exchanging data information. Background technique [0002] The standard SPI communication uses 4 IO ports to communicate, but there are too many IO port resources of the dedicated chip. The traditional SPI bus is a four-wire bus, including MISO master device data input, slave device data output; MOSI, master device data output, slave device data input; SCLK clock signal, generated by the master device; CS slave device enable signal, by Master device control. When exchanging data with the slave device, the master device will first select a device that wants to communicate with it through the CS chip select signal, and then send and receive data through the data line under the control of the SCLK clock signal, and the master device will control the entire communication process. If there are many slave devices, ...
Claims
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IPC IPC(8): G06F13/42
CPCG06F13/4291
Inventor 徐兴李湘春蓝龙伟范进生周晗
Owner 苏州锐联芯半导体有限公司