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Calibration of an interpolative divider using a virtual phase-locked loop

A technology of phase interpolator and phase-locked loop, which is applied in the direction of automatic power control, electrical components, multi-terminal pair network, etc., and can solve the problems of phase interpolator gain error, frequency divider, full-scale range mismatch, etc.

Pending Publication Date: 2021-03-26
SKYWORKS SOLUTIONS INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The gain error of the phase interpolator can cause a mismatch between the size of the least-significant bit of the integer divider and the full-scale range of the phase interpolator

Method used

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  • Calibration of an interpolative divider using a virtual phase-locked loop
  • Calibration of an interpolative divider using a virtual phase-locked loop
  • Calibration of an interpolative divider using a virtual phase-locked loop

Examples

Experimental program
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Embodiment Construction

[0017] refer to figure 1 , an embodiment of the clock product 100 includes a controller 102 and a clock generator 104 that monitor at least one receive using a clock signal REFCLK (eg, a clock signal generated using a crystal oscillator including an external crystal 101 coupled to the XA / XB inputs) and provide at least one output clock signal CLKOUT(N:1) and at least one clock quality signal, where P and N are integers greater than zero. In an embodiment of the clock product 100, the clock signal REFCLK is generated based on a stable source such as a crystal oscillator, a microelectromechanical structure (MEMS) oscillator, or other suitable low jitter source. Controller 102 provides configuration information to clock generator 104 using interface signal CTL. Clock generator 104 provides clock quality information (eg, LOSXA_XB or CLK_STATUS) to controller 102, which outputs one or more alert signals (eg, CLK_FAULT) based on the clock quality information.

[0018] refer to f...

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Abstract

A clock generator includes an interpolative divider including a phase interpolator and a multi-modulus divider. The interpolative divider is configured to generate an output clock signal based on a clock signal, a control code, and a phase interpolator calibration signal. The clock generator includes a calibration circuit configured to generate the phase interpolator calibration signal based on the clock signal, the output clock signal and a phase interpolator code. The calibration circuit includes a phase-locked loop configured to generate a digital phase error signal based on a reference timestamp signal and a timestamp signal based on the clock signal and the output clock signal. The calibration circuit includes an adaptive loop configured to generate the phase interpolator calibrationsignal based on the digital phase error signal.

Description

technical field [0001] The present invention relates to generating clock signals for electronic devices, and more particularly, to generating clock signals using interpolative dividers. Background technique [0002] A typical clock generator utilizes a phase locked loop provided with a reference signal from a source, such as a crystal oscillator, to generate an output clock signal having a frequency consistent with the target application. A technique for generating a clock signal having a frequency that is not reasonably related to the frequency of the reference clock signal divides the high frequency clock signal by a fraction using an interpolating divider. The interpolating divider includes an integer divider, a phase interpolator and a digital control circuit. The gain error of the phase interpolator can cause a mismatch between the size of a least-significant bit of the integer divider and the full-scale range of the phase interpolator. Therefore, a technique for cali...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03L7/093H03H7/06
CPCH03H7/06H03L7/093H03L7/0814H03L7/0992H03L7/23H03L7/081H03L7/197
Inventor 蒂莫西·A·蒙克道格拉斯·F·帕斯托雷洛
Owner SKYWORKS SOLUTIONS INC