Software and hardware joint verification system and method
A verification system and verification method technology, applied in the field of software and hardware joint verification system, can solve problems such as long development cycle
Active Publication Date: 2021-04-09
山东产研鲲云人工智能研究院有限公司
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[0005] The main purpose of the present invention is to provide a combined software and hardware verification system and method, aiming to solve the technical problem in the prior art that software and hardware are separated in most system developments, resulting in a long development cycle
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[0044]It will be appreciated that the specific embodiments described herein are intended to explain the present invention and is not intended to limit the invention.
[0045]The embodiment of the present invention provides a hardware and software combined verification system, referencefigure 1 ,figure 1 A structural block diagram of the first embodiment of the hardware and hardware joint verification system of the present invention.
[0046]In this embodiment, the hardware combined verification system driving software 10, a SYSTEMC analog-based memory 20 and a SYSTEMC simulated heterogeneous group 30, the driving software 10 is embedded in the memory 20 and the heterogeneous cluster 30. Systemc framework;
[0047]The drive software 10 is configured to transmit a drive instruction to the heterogeneous group 30 in accordance with preset verification requirements. In this embodiment, SYSTEMC is a soft / hardware synergistic design language, and the drive software 10 is embedded in the SYSTEMC f...
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The invention discloses a software and hardware joint verification system and method. The system comprises driving software, a memory based on systemc simulation and a heterogeneous cluster, wherein the driving software is embedded into the systemc framework; the driving software sends a driving instruction to the heterogeneous cluster according to a preset verification demand; the memory loads and stores to-be-verified data; the heterogeneous cluster extracts the to-be-verified data from the memory according to the driving instruction, calculates to obtain output data, and sends the output data to the driving software; and the driving software performs joint verification of software and hardware according to the output data. Heterogeneous clusters are simulated through systemc, driving software is embedded into a systemc framework, a model with the function equal to that of hardware is provided for the driving software, the control process of the driving software on the hardware is achieved, early-stage development and debugging of the software are assisted, and standard data are provided for the hardware. The technical problem that in the prior art, software and hardware are carried out separately in most system development, and consequently the development period is long is solved.
Description
Technical field[0001]The present invention relates to the field of integrated circuit design, and more particularly to a hardware and software combined verification system and method.Background technique[0002]The integrated circuit verification method widely used in the industrial community is: based on the simulation verification, formal verification, soft and hardware synergistic verification, based on the verification platform. Among them, simulation verification, formal verification is a typical verification method in hardware design. By establishing a reasonable complete test case, check whether RTL hardware design (register-level design) generates a corresponding response under certain excitation, completes from bottom-up unit test, integration test, and system testing.[0003]The design of the data stream architecture is related to the close cooperation of hardware and software. Because hardware and software design is separated in most system development, if the hardware and so...
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IPC IPC(8): G06F30/33G06F117/08
CPCG06F30/33G06F2117/08
Inventor 郭理源黄炯凯蔡权雄牛昕宇
Owner 山东产研鲲云人工智能研究院有限公司