Channel structure having protruding portion in three-dimensional memory device and method for forming same

Abstract

A three-dimensional (3D) memory device includes a memory stack including a conductive layer and a dielectric layer interleaved with the conductive layer, and a channel structure extending through the memory stack in a vertical direction. The channel structure has a plurality of protruding portions protruding in a lateral direction and respectively facing the conductive layer, and a plurality of normal portions respectively facing the dielectric layer without protruding in the lateral direction. The channel structure includes a plurality of blocking structures in the protruding portions, respectively, and a plurality of storage structures in the protruding portions, respectively, and over the plurality of blocking structures. A vertical dimension of each of the blocking structures is nominally the same as a vertical dimension of a respective one of the memory structures above the blocking structures.

Description

technical field [0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of manufacturing the same. Background technique [0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become increasingly challenging and expensive. As a result, the memory density of planar memory cells approaches an upper limit. [0003] 3D memory architectures can handle density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripherals for controlling signals to and from the memory array. Contents of the invention [0004] Embodiments of 3D memory devices and methods for forming the same are disclosed in this disclosure. [0005] In one example, a 3D memory device includes a memory stack includin...

AI Technical Summary

Problems solved by technology

However, planar processes and fabrication techniques become increasingly challenging and expensive as memory cell feature sizes approach the lower limit

Images