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Array substrate, manufacturing method thereof and display device

An array substrate and substrate substrate technology, applied in static indicators, static memory, instruments, etc., can solve the problems of unfavorable narrow borders and large space occupied by fan-out areas

Active Publication Date: 2021-04-13
HEFEI BOE ZHUOYIN TECH CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] Embodiments of the present invention provide an array substrate and its manufacturing method, and a display device, which are used to solve the problem that the existing PLG wiring occupies a large space in the fan-out area, which is not conducive to realizing a narrow frame

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  • Array substrate, manufacturing method thereof and display device
  • Array substrate, manufacturing method thereof and display device
  • Array substrate, manufacturing method thereof and display device

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Embodiment Construction

[0055] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

[0056] Please refer to figure 1 and figure 2 , an embodiment of the present invention provides an array substrate, including a base substrate (not shown in the figure) and a GOA circuit 10 and a PLG wiring 20 arranged in the peripheral area of ​​the base substrate, and the PLG wiring is used to connect The GOA circuit 10 and the source integrated circuit (IC), the PLG traces 20 are divided into at least two groups, the PLG traces 20 of the same group...

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Abstract

The invention provides an array substrate, a manufacturing method thereof and a display device. The array substrate comprises a substrate, a GOA circuit and PLG wires, wherein the GOA circuit and the PLG wires are arranged on the substrate; the PLG wires are used for connecting the GOA circuit and a source IC, the PLG wires are divided into at least two groups, the PLG wires in the same group have the same line width, and the PLG wires in different groups have different line widths; a GOA signal comprises a cascade signal and a non-cascade signal; at least two PLG wire groups comprise a first PLG wire group and at least one second PLG wire group, the first PLG wire group transmits cascade signals, the second PLG wire group transmits non-cascade signals, the line width of the first PLG wire group is smaller than that of the second PLG wire group, and the first PLG wire group is located on the side, away from the display area of the substrate, of the second PLG wire group. According to the invention, the line width of some groups of PLG wires can be set to be smaller, so as to reduce the area occupied by the PLG wires.

Description

technical field [0001] Embodiments of the present invention relate to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] In the display industry, in order to reduce the material cost of the display device and realize the narrow frame design of the display device, more gate drive circuits adopt GOA technology (Gate Driver on Array, array substrate row drive, that is, integrate the gate drive circuit on the array substrate). [0003] The GOA circuit can be connected to the source integrated circuit (IC) through a PLG trace (Propel Link Gate, connected to the gate) to receive a signal output from the source IC. When the display device is a high PPI (Pixels Per Inch, pixel density) display device, the number of PLG lines is large, and the area occupied in the fan-out area (layout) is large, which is not conducive to realizing a narrow frame. Contents of the invention ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G09G3/3233
CPCG09G3/3233G11C19/28G09G2300/0408G09G2300/0426G09G2310/0286G09G3/20G09G3/3225G09G2310/08G11C19/287
Inventor 吴仲远李永谦袁粲冯雪欢袁志东
Owner HEFEI BOE ZHUOYIN TECH CO LTD
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