Super-junction silicon carbide semiconductor device and method for manufacturing super-junction silicon carbide semiconductor device
A super-junction silicon carbide and semiconductor technology, applied in the field of super-junction silicon carbide semiconductor devices, can solve the problems of shortening the depletion layer, increasing the resistance, increasing the thickness of the n-type drift layer, etc.
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Embodiment approach 1
[0077] The semiconductor device of the present invention will be described taking an SJ-MOSFET as an example. figure 1 It is a cross-sectional view showing the structure of the silicon carbide SJ-MOSFET of the first embodiment. figure 1 The silicon carbide SJ-MOSFET300 shown is on the front side (p - An SJ-MOSFET having a MOS (Metal Oxide Semiconductor, Metal Oxide Semiconductor) gate on the surface on the side of the base region 16 . exist figure 1 In , only two unit cells (functional units of elements) are shown, and illustration of other unit cells adjacent to them is omitted.
[0078] no + Type silicon carbide substrate (silicon carbide semiconductor substrate of the first conductivity type) 1 is a silicon carbide single crystal substrate doped with, for example, nitrogen (N). no - Type drift layer (the first semiconductor layer of the first conductivity type) 2 is impurity concentration ratio n + Type silicon carbide substrate 1 has a low impurity concentration, ...
Embodiment approach 2
[0107] Next, the structure of the semiconductor device according to Embodiment 2 will be described. Figure 9 It is a cross-sectional view showing the structure of a silicon carbide SJ-MOSFET according to the second embodiment. Such as Figure 9 As shown, the difference between the silicon carbide SJ-MOSFET 301 of the second embodiment and the silicon carbide SJ-MOSFET 300 of the first embodiment is that an n-type high-concentration region (the third semiconductor layer of the first conductivity type) is provided on the surface of the parallel pn region 33 ) 5, and selectively set p in the n-type high-concentration region 5 + type region (the second semiconductor region of the second conductivity type) 3 .
[0108] The n-type high-concentration region 5 is the impurity concentration ratio n + type SiC substrate 1 lower and lower than n - The type drift 2 is high, and the n-type drift layer is doped with a high concentration of nitrogen, for example. The n-type high-concen...
Embodiment approach 3
[0126] Next, the structure of the semiconductor device according to Embodiment 3 will be described. Figure 14 It is a cross-sectional view showing the structure of a silicon carbide SJ-MOSFET according to the third embodiment. Such as Figure 14 As shown, the difference between the silicon carbide SJ-MOSFET 302 of the third embodiment and the silicon carbide SJ-MOSFET 301 of the second embodiment is that the p-type column region 30 is arranged directly under the trench 23 (p at the bottom of the trench 23 + type region 3 and n - type drift 2).
[0127] In the third embodiment, the pitch of the parallel pn regions 33 (the width between the p-type column regions 30 ) is half that of the first and second embodiments. For example, the width of the p-type pillar region 30 can be set to 1.5 μm, and the width of the n-type pillar region 31 can be set to 1.0 μm. Therefore, the impurity concentration of the n-type pillar region 31 can be made higher than that of Embodiment 1 and E...
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Abstract
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