Chained redundant board-level clock timing method and device
A redundant board-level and clock technology, applied in the direction of generating/distributing signals, instruments, electrical digital data processing, etc., can solve the problems of complex, unavoidable, and overloaded backplane wiring.
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[0033] see figure 1 , figure 1 It is a schematic flowchart of a method for calibrating a chained redundant board-level clock in an embodiment of the present invention.
[0034] Such as figure 1 Shown, a kind of chained redundant board-level clock timing method, described method comprises:
[0035] S11: The main board transmits the serial differential signal from the first sub-card at one end of the series-connected sub-cards to the next sub-card one by one, until the last sub-card returns the serial differential signal to the main board;
[0036] In the specific implementation process of the present invention, the serial differential signals include group A serial differential signals and B serial differential signals; The next sub-cards are transmitted one by one until the last sub-card at the end returns the serial differential signal to the main board, including: the main board transfers the A group of serial differential signals from the first sub-card at the head end o...
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