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Chained redundant board-level clock timing method and device

A redundant board-level and clock technology, applied in the direction of generating/distributing signals, instruments, electrical digital data processing, etc., can solve the problems of complex, unavoidable, and overloaded backplane wiring.

Pending Publication Date: 2021-04-20
ELECTRIC POWER RES INST OF GUANGXI POWER GRID CO LTD +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Board-level time synchronization in the system generally uses a parallel bus to connect the clock board of the main board to each sub-board through the backplane. However, when the number of sub-boards is large, signal integrity problems caused by excessively long drives and heavy loads are unavoidable. Timing may go wrong
Another point-to-point mode, although it can solve the signal integrity problems caused by too many sub-boards and heavy loads, as the number of sub-boards increases, it will lead to too many signals on the main clock board and complex wiring on the backplane. question

Method used

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  • Chained redundant board-level clock timing method and device
  • Chained redundant board-level clock timing method and device

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Experimental program
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Embodiment

[0033] see figure 1 , figure 1 It is a schematic flowchart of a method for calibrating a chained redundant board-level clock in an embodiment of the present invention.

[0034] Such as figure 1 Shown, a kind of chained redundant board-level clock timing method, described method comprises:

[0035] S11: The main board transmits the serial differential signal from the first sub-card at one end of the series-connected sub-cards to the next sub-card one by one, until the last sub-card returns the serial differential signal to the main board;

[0036] In the specific implementation process of the present invention, the serial differential signals include group A serial differential signals and B serial differential signals; The next sub-cards are transmitted one by one until the last sub-card at the end returns the serial differential signal to the main board, including: the main board transfers the A group of serial differential signals from the first sub-card at the head end o...

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PUM

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Abstract

The invention discloses a chained redundant board-level clock timing method and device. The method comprises steps that a mainboard transmits a serial differential signal from a first sub-card at one end of sub-cards connected in series to a next sub-card one by one till the last sub-card returns the serial differential signal to the mainboard; the daughter card analyzes the clock information frame according to the serial differential signal and performs CRC to obtain clock information; and clock synchronization of the daughter card is carried out according to the clock information and the transmission frame delay, and the clock information is sent to the next daughter card through a clock data differential signal in a serial differential signal without modification. The method is advantaged in that automatic synchronization of the daughter card clock can be realized, and normal transmission of the daughter card clock information is ensured.

Description

technical field [0001] The invention relates to the technical field of power system testing equipment, in particular to a method and device for calibrating a chained redundant board-level clock. Background technique [0002] In the power system, acquisition, control, management, testing and other equipment generally use the backplane plus sub-boards for various functions. These sub-boards need to be synchronized to the internal unified clock. Board-level time synchronization in the system generally uses a parallel bus to connect the clock board of the main board to each sub-board through the backplane. However, when the number of sub-boards is large, signal integrity problems caused by excessively long drives and heavy loads are unavoidable. Timing may go wrong as a result. Another point-to-point mode, although it can solve the signal integrity problems caused by too many sub-boards and heavy loads, as the number of sub-boards increases, it will lead to too many signals on ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F1/12G06F13/20
Inventor 周柯王晓明李肖博巫聪云赵继光李文伟习伟林翔宇姚浩彭博雅宋益
Owner ELECTRIC POWER RES INST OF GUANGXI POWER GRID CO LTD