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Heterogeneous acceleration system and method based on CTPN network

A technology for accelerating systems and networks, applied in biological neural network models, architectures with a single central processing unit, neural architectures, etc. Effect

Active Publication Date: 2021-04-30
SHANGHAI JIAO TONG UNIV +1
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  • Abstract
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  • Application Information

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Problems solved by technology

However, its complex network structure makes hardware acceleration difficult to achieve due to resource constraints, so implementing heterogeneous acceleration for this network is an effective solution

Method used

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  • Heterogeneous acceleration system and method based on CTPN network
  • Heterogeneous acceleration system and method based on CTPN network
  • Heterogeneous acceleration system and method based on CTPN network

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Embodiment

[0044] The invention includes a CPU-FPGA heterogeneous execution optimization sub-graph segmentation method for CTPN and similar structure networks. The heterogeneous execution optimization subgraph segmentation method of the present invention balances the consumption of hardware resources and the transmission cost between hardware, and adjusts the functions of the network layer on the execution device, so that both FPGA and CPU have better acceleration effects.

[0045] The heterogeneous execution optimization subgraph segmentation method divides the CTPN network into three main subgraphs: figure 1 ,son figure 2 And child image 3 . The subgraphs run on different processing devices and exchange data. The optimized subgraph segmentation and heterogeneous execution can reduce the overall execution time of the CTPN network and improve the acceleration performance.

[0046]The heterogeneous execution of the present invention refers to the joint execution of the accelerator in...

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Abstract

The invention provides a heterogeneous acceleration system and method based on a CTPN network. The heterogeneous acceleration system comprises a CPU end and an FPGA end. the FPGA end comprises a first sub-graph and a second sub-graph, and the CPU end comprises a third sub-graph; the first sub-graph comprises a CTPN network CNN part, the second sub-graph comprises an RNN part, and the third sub-graph comprises a CTPN network remaining part; the first sub-graph and the second sub-graph are executed at an FPGA end, and the third sub-graph is executed at a CPU end; the output of the FPGA end is used as the input of the third sub-graph; and the CPU end finally realizes network inference and obtains a final result. According to the system and method, the deduction speed of the CTPN network can be greatly improved under the condition that the precision is slightly reduced, so that the accelerator can better realize a real-time scene character recognition function.

Description

technical field [0001] The present invention relates to the field of neural network accelerators, in particular to a CTPN network-based heterogeneous acceleration system and method. Background technique [0002] Connectionist Text Proposal Network (CTPN), a neural network proposed in 2016 for scene text recognition, is actually a neural network based on CNN+RNN structure. Among them, CNN is used to extract deep features, and RNN is used for character sequence feature recognition. This network takes advantage of the respective advantages of CNN and RNN. RNN also uses bidirectional LSTM (BiLSTM) to recognize and infer text from different directions of the picture, which greatly improves the accuracy of text detection. Since various applications of scene text recognition require network recognition and inference to be as fast as possible, it is particularly important to implement hardware acceleration for CTPN networks. However, its complex network structure makes hardware ac...

Claims

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Application Information

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IPC IPC(8): G06F15/78G06N3/04
CPCG06F15/7871G06N3/044G06N3/045
Inventor 蒋剑飞蔡亮郭怡良董峰虞科华陈可
Owner SHANGHAI JIAO TONG UNIV
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