Method for preparing three-dimensional memory

Abstract

The present application provides a method for preparing a three-dimensional memory, the method comprising: forming a source sacrificial layer on a substrate, a stacked structure located above the source sacrificial layer, and penetrating through the stacked structure and the source sacrificial layer and extending to The channel hole in the substrate; the functional layer and the amorphous silicon layer are sequentially formed on the inner wall of the channel hole; the induced metal film is formed on the top surface of the stacked structure away from the substrate, so that the induced metal film and the amorphous silicon layer contacting; inducing the crystallization of the amorphous silicon layer to form a crystalline silicon channel layer; and removing the source sacrificial layer and a portion of the functional layer adjacent to the substrate to partially expose the substrate and the crystalline silicon channel layer; and in the A source connection layer is formed on the exposed substrate to contact the exposed crystalline silicon channel layer. Accordingly, the carrier mobility of the channel structure of the three-dimensional memory can be improved, thereby improving the battery current of the semiconductor device as a whole.

Description

technical field [0001] The present application generally relates to the field of semiconductor design and manufacturing, and more particularly, to a method for improving the fabrication process of a channel structure in a three-dimensional memory. Background technique [0002] As the number of stacked layers in a three-dimensional memory (for example, 3D NAND) increases, the aspect ratio (AR) of the channel increases, and the quality requirements for the polysilicon channel layer become higher and higher. [0003] In the prior art manufacturing method of the three-dimensional memory, the polysilicon channel layer is usually formed by solid phase crystallization (Solid Phase Crystallization, SPC) or thin film deposition method. [0004] However, the crystallinity of polysilicon produced by solid phase crystallization is not ideal, such as uneven grain size, high grain boundary barrier height, etc., resulting in low carrier mobility (high impedance). Usually, additional hydro...

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Problems solved by technology

[0005] In addition, the grain morphology of polysilicon deposited by thin film deposition method is not good (for example, V-shape), and usually contains a high density of micro-twin crystal defects, the grain size is small, the carrier mobility is not large enough, and make it subject to certain limitations in device application

[0006] At the same time, due to the increase in the stacking amount of the stacked structure, the channel length becomes longer, and the resistance of the polysilicon channel layer with low carrier mobility will increase more significantly, so that the conduction current of the channel structure is significantly reduced.

This may limit the increase in the bit density of 3D memory, and may also affect the stability of the threshold voltage (Vt), eventually leading to poor performance of 3D memory.

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