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Chip and wafer for wafer level testing

A wafer-level, chip-based technology, applied in semiconductor/solid-state device testing/measurement, electrical components, electrical solid-state devices, etc., can solve the problem of long probe card production cycle, slowing down the wafer chip testing process, and increasing production costs And other issues

Pending Publication Date: 2021-05-28
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the production cycle of the probe card is long, and different probe cards are provided for chips with different pad layout structures, which not only increases the production cost, but also slows down the testing process of the wafer chip

Method used

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  • Chip and wafer for wafer level testing
  • Chip and wafer for wafer level testing
  • Chip and wafer for wafer level testing

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Embodiment Construction

[0027] The technical solutions in this application will be clearly and completely described below in conjunction with the accompanying drawings. Apparently, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0028] In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, use a specific orientati...

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PUM

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Abstract

The invention relates to the field of wafer level testing, in particular to a chip and a wafer for wafer level testing. The chip used for the wafer level testing comprises a semiconductor substrate, a semiconductor device active region, an interconnection layer, an interconnection bonding pad, and a test bonding pad; and the semiconductor substrate comprises a front surface and a back surface which are opposite to each other; the semiconductor device active region is formed on the front surface of the semiconductor substrate; the interconnection layer is formed on the front surface of the semiconductor substrate and comprises an interconnection region and a test region; the interconnection bonding pad is formed in the interconnection region and is electrically coupled with the active region of the semiconductor device through an interconnection structure; and the test bonding pad is formed in the test area and is electrically coupled with the interconnection bonding pad through a bonding wire. The wafer comprises a plurality of chips used for wafer level testing and arranged in an array mode, and a scribing groove is formed between every two adjacent chips. According to the invention, the problem that probe cards with different structures need to be provided for matching and coupling with chips with different bonding pad arrangement structures in the prior art can be solved.

Description

technical field [0001] The present application relates to the field of wafer-level testing, in particular to a chip and wafer for wafer-level testing. Background technique [0002] Before the wafer leaves the factory, the chips on the wafer need to be tested to judge whether the performance of the chip is good or bad. In the wafer chip test, the target wafer is installed on the test machine, and the pads of the target chip on it are electrically coupled with the test machine through the probe card, and the test machine executes the test instructions to complete the test. The testing process of the target chip. After testing a chip, the probe card is electrically coupled with the pad of the next target chip to continue testing. [0003] In the related art, the number and position of pads on different chips are different. Therefore, during the wafer-level testing process, it is necessary to provide probe cards with different structures to match and couple with chips with dif...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/544H01L21/66
CPCH01L22/14H01L22/34
Inventor 张庆文
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP