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Multi-bit in-memory computing unit, array and device

A computing unit and computing array technology, which is applied in computing, information storage, static memory, etc., can solve the problems of large area and insufficient calculation accuracy, and achieve the effect of improving calculation accuracy

Pending Publication Date: 2021-06-01
中科南京智能技术研究院
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The traditional 8T SRAM (Static Random-Access Memory) structure has a large number of transistors and a large area, and there is also the problem that the calculation accuracy is not high enough

Method used

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  • Multi-bit in-memory computing unit, array and device
  • Multi-bit in-memory computing unit, array and device

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Embodiment Construction

[0032] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0033] The purpose of the present invention is to provide a multi-bit in-memory calculation unit, array and device, which improves the calculation accuracy.

[0034] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0035] figure 1 It is a schematic diagram of a multi-...

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Abstract

The invention relates to a multi-bit in-memory calculation unit, array and device, the multi-bit in-memory calculation unit comprises a plurality of storage parts and one calculation part, each storage part comprises four transistors used for storing weights, each calculation part comprises two transistors, and each calculation part is used for weighted calculation of the stored weights and input data. According to the invention, multiply-accumulate operation of 2-bit input data and weights is realized, and the calculation precision is improved.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a multi-bit in-memory computing unit, array and device. Background technique [0002] Deep Convolutional Neural Networks (DCNNs) are developing rapidly in artificial intelligence and other fields. With its gradual development, more and more issues such as size, efficiency, and energy consumption need to be considered. In the traditional calculation process, the weight is moved between the memory and the operation unit, which does not meet the requirements of low power consumption. In-memory computing (IMC) is increasingly attractive for DCNN acceleration. The traditional 8T SRAM (Static Random-Access Memory) structure has a large number of transistors and a large area, and there is also the problem that the calculation accuracy is not high enough. Contents of the invention [0003] The purpose of the present invention is to provide a multi-bit in-memory calculatio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/063G11C7/10G11C7/12G11C8/08G11C8/10G06F7/544
CPCG06N3/063G11C7/1006G11C7/12G11C8/08G11C8/10G06F7/5443Y02D10/00
Inventor 乔树山陶皓尚德龙周玉梅
Owner 中科南京智能技术研究院