Compression LSTM accelerator and acceleration method based on FPGA

Abstract

The invention discloses a compressed LSTM accelerator based on an FPGA and an acceleration method. The FPGA accelerator internally comprises a plurality of calculation units, a storage unit and a control unit. The method comprises the steps of: detecting a non-zero weight element value of the hidden node sparse weight matrix and a corresponding column index value by using a non-zero detection module; finding a corresponding excitation value according to the column index value by utilizing a weight decoding module; sending the plurality of non-zero weight element values and the plurality of excitation values to a matrix vector multiplication module for operation to obtain result vectors of the four gates; and enabling the Element operation module to calculate a cell state value and an output value at the current moment according to the result vectors of the four gates. In one calculation period, only the non-zero weight element value of each gate and the corresponding excitation value are multiplied, so that each matrix vector multiplication module is not idle in one calculation period, meanwhile, the time of a single calculation period is shortened, the calculation performance and throughput of the accelerator are improved, and meanwhile, the on-chip cache of the FPGA is saved.

Description

technical field [0001] The invention relates to the field of neural network computer hardware acceleration, in particular to an FPGA-based compressed LSTM accelerator and an acceleration method. Background technique [0002] At present, LSTM networks have achieved great success in various applications such as machine translation, multilingual processing, handwriting generation, and image caption generation. The higher the value, the more important it is to choose the right accelerator platform. FPGA can design a hardware structure suitable for neural network algorithms, and developers can connect the logic units inside FPGA through programmable connections according to their own needs to realize corresponding functions. At the same time, FPGA can design the hardware architecture according to the characteristics of the algorithm when designing the hardware acceleration of the neural network algorithm. And in terms of comprehensive computing and power consumption, FPGA has a...

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Problems solved by technology

[0004] At present, FPGA-based LSTM accelerators generally use parallel computing and parallel reading data to improve the acceleration performance of the accelerator. If the above-mentioned sparse weight matrix is ​​directly involved in the calculation, due to the existence of multiple zero elements, many computing units are idle in one computing cycle, thus lead to overall inefficiency

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