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Data processor, method, chip and electronic equipment

A data processor and data technology, applied in the computer field, can solve the problems of increasing the power consumption of the data processor and reducing the versatility of the data processor.

Pending Publication Date: 2020-01-14
SHANGHAI CAMBRICON INFORMATION TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, existing data processors can only perform multiplication and accumulation operations on data with the same bit width, which reduces the versatility of the data processor
In addition, in the prior art, multiple multiplication results need to be accumulated separately to realize the multiplication and accumulation operation, thereby increasing the power consumption of the data processor

Method used

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  • Data processor, method, chip and electronic equipment
  • Data processor, method, chip and electronic equipment
  • Data processor, method, chip and electronic equipment

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Embodiment Construction

[0065] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0066] The data processor provided by this application can be applied to AI chips, field programmable gate array FPGA (Field-Programmable Gate Array, FPGA) chips, or other hardware circuit devices for multiplication processing or multiplication-accumulation processing. The structure diagram of the processor is shown in figure 1 and 2 shown.

[0067] like figure 1 as shown, figure 1 A structural diagram of a data processor provided for an embodiment. like figure 1As shown, the data processor includes: a first multiplication circuit 11, a second multiplication circuit ...

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Abstract

The invention provides a data processor, a data processing method, a chip and electronic equipment. The data processor comprises a first multiplication circuit, a second multiplication circuit and a partial product switching circuit. The output end of the first multiplication circuit is connected with the first input end of the partial product switching circuit; the first output end of the partialproduct switching circuit is connected with the first input end of the second multiplication circuit; the output end of the second multiplication operation circuit is connected with the second inputend of the partial product exchange circuit, the second output end of the partial product exchange circuit is connected with the input end of the first multiplication operation circuit, the data processor can achieve multiplication operation and multiply-accumulate operation, and therefore the universality of the data processor is improved; moreover, the data processor can complete multiply-accumulate operation without performing accumulate operation on the multiply operation result again, and multiply operation or multiply-accumulate operation can be directly realized through one operation process, so that the power consumption of the data processor is reduced.

Description

technical field [0001] The present application relates to the field of computer technology, and in particular, to a data processor, method, chip and electronic device. Background technique [0002] With the continuous development of digital electronic technology, the rapid development of various artificial intelligence (AI) chips has higher and higher requirements for high-performance data processors. Among them, the data processors are multipliers, adders or multipliers. accumulator. Neural network algorithm is one of the algorithms widely used in smart chips. Multiply-accumulate operation by multiply-accumulator is a common operation in neural network algorithm. [0003] Usually, the data processor uses multiple multipliers with the same input data bit width or different data bit widths to perform parallel multiplication operations to obtain multiple multiplication results, and then accumulate the multiple multiplication results through the adder to obtain The target mul...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/523G06N3/063
CPCG06F7/523G06N3/063
Inventor 不公告发明人
Owner SHANGHAI CAMBRICON INFORMATION TECH CO LTD