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DDR arbiter with multiple user interfaces and DDR controller chip

A user interface and multi-user technology, applied in the field of DDR arbiter and DDR controller chip, can solve the problems of low design efficiency, low design versatility, repetitive labor, etc., achieve high design versatility, improve design efficiency, reduce The effect of repeating the design

Pending Publication Date: 2021-06-11
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the design versatility of this method is not high, requiring repeated labor for different user interfaces, and the design efficiency is low

Method used

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  • DDR arbiter with multiple user interfaces and DDR controller chip
  • DDR arbiter with multiple user interfaces and DDR controller chip
  • DDR arbiter with multiple user interfaces and DDR controller chip

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Embodiment Construction

[0030] The core of the present application is to provide a multi-user interface DDR arbiter and DDR controller chip, so as to effectively improve the design versatility and efficiency of DDR.

[0031] In order to describe the technical solutions in the embodiments of the present application more clearly and completely, the technical solutions in the embodiments of the present application will be introduced below in conjunction with the drawings in the embodiments of the present application. Based on the embodiments in this application, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the scope of protection of this application.

[0032] see figure 1 As shown, the embodiment of the present application discloses a DDR arbiter of a multi-user interface, which mainly includes:

[0033] User interface parameter module 101: used to define the number of user bus interfaces and the parameters of each user bus interface t...

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Abstract

The invention discloses a DDR arbiter with a multi-user interface and a DDR controller chip. The DDR arbiter with the multi-user interface comprises: a user interface parameter module, which is used for defining the number of user bus interfaces and parameters of each user bus interface through system parameters; a user bus interface module, which is used for realizing each user bus interface based on system parameter instantiation; a queue caching module, which is used for caching access commands sent by the user bus interfaces and sequentially sending the access commands to the DDR controller according to an arbitration result; and an arbitration logic module, which is used for arbitrating the processing sequence of each access command stored in the queue cache module to generate an arbitration result. The parameters of each user bus interface are flexibly defined through the system parameters, so that the invention has relatively high design universality, and repeated design among different user bus interfaces is favorably reduced. Moreover, a new chip design can be realized only by slightly modifying related system parameters, so that the design efficiency is greatly improved.

Description

technical field [0001] The present application relates to the technical field of storage, in particular to a DDR arbiter and a DDR controller chip of a multi-user interface. Background technique [0002] In order to solve the needs of multiple users to access DDR (Double Data Rate, double-rate synchronous dynamic random access memory), arbitration is usually carried out before entering the DDR controller, and the arbitrator determines the respective access rights and order of multiple users, so as to complete them one by one. Multiple user interface access to DDR. [0003] At present, the common method of multi-user interface access is that the DDR arbiter writes the commands of each user interface to access the DDR into the cache, and then combines the characteristics of the DDR read and write timing sequence to sort the command processing sequence in a targeted manner, and complete the sequence according to the sorting results. DDR access. However, the generality of the ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16
CPCG06F13/1605G06F13/1668
Inventor 贾学强
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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