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Bottom-up clock synchronization device and system

A clock synchronization, bottom-up technology, applied in the field of communication, can solve the problem of high cost

Pending Publication Date: 2021-06-22
北京方天鸿瑞科技有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The object of the present invention is to provide a bottom-up clock synchronization device and system to improve the problem of high cost in the prior art

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  • Bottom-up clock synchronization device and system

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Embodiment Construction

[0023] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. The components of the embodiments of the invention generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations.

[0024] Accordingly, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art wi...

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Abstract

The invention provides a bottom-up clock synchronization device and system, and relates to the technical field of communication. The bottom-to-top clock synchronization device includes a baseband processing circuit, a clock circuit, a logic circuit, and a processing circuit. The baseband processing circuit can receive an air interface synchronization signal sent by a base station and can process the air interface synchronization signal to obtain a middle period pulse and a starting point of a wireless frame period. The clock circuit carries out closed-loop negative feedback control processing on the processed signal of the middle-period pulse to obtain a short-period pulse. The logic circuit performs timing output according to the end periodic pulse, and meanwhile, the processing circuit sends a time information request to a server according to a starting point of a wireless frame period obtained by processing of the baseband processing circuit, and then calculates the time from the next pulse per second to a rising edge after a result returned by the server is obtained; and therefore, the logic circuit can finally determine accurate clock information.

Description

technical field [0001] The present invention relates to the technical field of communications, in particular to a bottom-up clock synchronization device and system. Background technique [0002] Speaking of synchronization, everyone naturally thinks of the synchronization mechanism from top to bottom, from the center to the edge. The clock source is located in the center and sends synchronization signals to the periphery to form a synchronization network. With the development of communications, especially mobile communications, from 3G to 4G, multiple access methods have emerged from frequency division (FDD) to time division (TDD), and a higher-precision clock has been introduced through satellite systems such as GPS or Beidou in base stations accessing the network . Since the clock quality of the wireless base station is better than the clock signal quality of the wireless controller or the core network, the waterfall transmission method in which the clock is gradually dis...

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Application Information

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IPC IPC(8): H04W56/00H04J3/06
CPCH04W56/0015H04J3/0644Y02D30/70
Inventor 周艳秋蒋纯波薛玉旺吕英中徐盛威
Owner 北京方天鸿瑞科技有限公司
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