Semiconductor structure and method of forming integrated circuit structure

Abstract

The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a substrate having a front side and a back side; a gate stack formed on the front side of the substrate and disposed on an active region of the substrate; a first source / drain part formed on the active region and disposed at an edge of the gate stack; a backside power rail formed on the back side of the substrate; and a backside contact part interposed between a backside power rail and the first source / drain part, and electrically connecting the backside power rail to the first source / drain part. The backside contact part further includes a first silicide layer on the back side of the substrate. Embodiments of the invention also relate to a method of forming an integrated circuit structure.

Description

technical field [0001] Embodiments of the invention relate to semiconductor structures and methods of forming integrated circuit structures. Background technique [0002] Integrated circuits have been developed as advanced technologies with smaller feature sizes such as 7nm, 5nm, and 3nm. In these advanced technologies, the gate pitch (spacing) keeps shrinking, thus causing a link to gate bridge problems. Furthermore, three-dimensional transistors with fin-shaped active regions are generally required to enhance device performance. Those three-dimensional field effect transistors (FETs) formed on fin-type active regions are also called FinFETs. FinFETs require narrow fin widths for short channel control, which results in smaller source / drain regions compared to planar FETs. This will reduce the alignment margin and cause further shrinking device pitch and increasing packing density. As devices scale down, power lines are formed on the backside of the substrate. However, ...

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Problems solved by technology

However, existing backside power rails still face challenges including routing resistance, alignment margins, layout flexibility, and packaging density

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