One-dimensional phase unwrapping algorithm implemented on FPGA

Abstract

The invention discloses a one-dimensional phase unwrapping algorithm implemented on an FPGA , which comprises the following steps of: adopting a data delay operation to enable a wrapped phase Phase_wrapped to be aligned with a time sequence of an increase and decrease flag bit FLAG, and unwrapping the wrapped phase to obtain a primary phase unwrapping result Phase_unwrapped_reg0; and then, performing phase unwrapping on the initial phase unwrapping result (Phaseun_wrapped_reg0 at a single-point truncation position, so that the unwrapped phase (Phaseun_wrapped) can be obtained. According to the method, a multiplier does not need to be called, the phase unwrapping algorithm can be realized on an FPGA hardware platform only through delay, addition and subtraction operations, and the robustness of the algorithm is enhanced.

Description

technical field [0001] The invention belongs to the field of radar forward modeling simulation, and in particular relates to a one-dimensional phase unwrapping algorithm realized on FPGA. Background technique [0002] Phase unwrapping (the data Phase Unwrapping) is a classic signal processing problem, which refers to recovering the original phase value from the value interval (π,π] or (0,2π]. When using the arctangent function to calculate the phase, The phase actually extracted is the wrapped phase value wrapped in a periodic phase interval, not the real phase. Restoring the wrapped phase to a real continuous phase is the phase expansion. The traditional algorithm assumes that the wrapped phase signal is x w (n), the unfolded phase is x u (n): make x u (n)=x w (n); Calculate the difference ΔPhase=x of the data w (n)-x w (n-1); if the data difference ΔPhase>π, then x u (n) 2π is subtracted from the current point and all subsequent points; if the data difference ΔPha...

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Problems solved by technology

The traditional algorithm assumes that the wrapped phase signal is x w (n), the unfolded phase is x u (n): make x u (n)=x w (n); Calculate the difference ΔPhase=x of the data w (n)-x w (n-1); if the data difference ΔPhase>π, then x u (n) 2π is subtracted from the current point and all subsequent points; if the data difference ΔPhaseu (n) Add 2π to the current point and all subsequent points; the above algorithm is easy to implement on a computer, but when implemented on an FPGA, it needs to consume more multiplier resources and the implementation steps are cumbersome

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