Semiconductor packaging structure and manufacturing method thereof
A packaging structure and semiconductor technology, which is applied in the fields of semiconductor/solid-state device manufacturing, semiconductor devices, and semiconductor/solid-state device components, etc., and can solve the problems of bare semiconductor chips and shedding of packages.
Pending Publication Date: 2021-07-09
ADVANCED SEMICON ENG INC
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However, when the thickness of the package covering the semiconductor die is thinned to a lower value by grinding, the package may be detached from the semiconductor die, resulting in the semiconductor die being exposed.
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[0037] Common reference numbers are used throughout the drawings and the detailed description to refer to the same or similar components. Embodiments of the present disclosure will be better understood from the following detailed description taken in conjunction with the accompanying drawings.
[0038] The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to illustrate certain aspects of the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include additional features that may Embodiments formed or disposed between the first feature and the second feature such t...
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Abstract
The invention relates to a semiconductor package structure and a method for manufacturing the same. The semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure electrically connects the conductive pad of the semiconductor die and defines a recessed portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.
Description
technical field [0001] The present disclosure relates to a semiconductor package structure and a manufacturing method, and to a semiconductor package structure including at least one pillar structure for vertical electrical connection and a method for manufacturing the semiconductor package structure. Background technique [0002] For a semiconductor package such as a fan-out chip on substrate (FOCoS) package, a semiconductor die may be covered by an encapsulant. In order to reduce the overall thickness of the semiconductor package, the package body may be thinned by, for example, grinding. However, when the thickness of the package covering the semiconductor die is thinned to a lower value by grinding, the package may fall off from the semiconductor die, thereby causing the semiconductor die to be exposed. SUMMARY OF THE INVENTION [0003] In some embodiments, a semiconductor package structure includes a semiconductor die and at least one pillar structure. The semicondu...
Claims
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IPC IPC(8): H01L23/482H01L23/31H01L21/48H01L21/56
CPCH01L23/482H01L23/4824H01L23/3114H01L21/4814H01L21/56H01L21/6835H01L2221/68345H01L2221/68359H01L23/3128H01L25/0652H01L2225/06517H01L2225/06572H01L2224/214H01L2224/94H01L2224/81005H01L2224/73204H01L2924/18161H01L2224/92125H01L2224/97H01L2224/32225H01L2924/15311H01L2224/83005H01L2224/16238H01L24/16H01L24/32H01L24/73H01L24/19H01L2224/73267H01L2924/18162H01L2224/04105H01L2224/12105H01L2224/83H01L2224/81H01L21/76871H01L2224/02371H01L23/3107H01L24/05H01L23/5283H01L23/5226
Inventor 张勇舜谢孟伟李德章
Owner ADVANCED SEMICON ENG INC