Video image display processing control device and method and display terminal

Abstract

The invention provides a video image display processing control device. The device comprises an input decoding module, a pre-stage scaling engine module, a first YCbCr-to-RGB module, a first layer superposition module, an RGB-to-YCbCr module, a first selector, a rotation control module, a frame buffer controller, an arbiter, a post-stage scaling engine module, a second selector, a second YCbCr-to-RGB module, a second layer superposition module, an AOSD / OSD module, a third selector and a time schedule controller. According to the selection control signal, the layer data output by the OSD / AOSD module is overlapped on the image data before the rotation processing or the image data after the post-scaling processing. The device does not need a high-cost integrated CPU (Central Processing Unit) large system, and is low in cost and good in image display processing effect.

Description

technical field

[0001] The present invention relates to the technical field of digital image processing, in particular to a video image display processing control device, method and display terminal. Background technique

[0002] In the fields of in-vehicle multimedia systems and surveillance cameras, the application of digital images is becoming more and more extensive, and the requirements for video image quality are getting higher and higher. In display chips such as monitors, it is a trend for video sources to develop from traditional standard definition to high definition. In traditional single display chips of this type, the received input signal (such as ITU656 / ITU601 / RGB888, etc.) After generating a series of timing sequences that match the screen, these chips usually do not have a frame buffer, that is, the output frame rate is consistent with the input frame rate. When the input is a standard-definition CVBS signal, since the input frame rate is 50 / 60Hz, The outpu...

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