Parallel method and device for convolution calculation and data loading of neural network accelerator

Abstract

The invention discloses a parallel method and device for neural network accelerator convolution calculation and data loading. The parallel mode requires two input feature maps and convolution kernel cache blocks respectively, and the input feature maps and 64 convolution kernels are loaded according to the load. The input length is stored in each cache sub-block in turn, and the convolution calculation is performed efficiently while the data loading of the next group of 64 convolution kernels is realized. A general neural network requires hundreds or thousands of convolution kernels, and storing all of them on-chip requires a large amount of storage space, which will result in a larger chip area and a corresponding increase in manufacturing costs. The present invention significantly reduces on-chip storage space while ensuring efficient calculation of convolution, reduces chip area, and further reduces chip cost. Its implementation method is simple, flexible and controllable, and has nothing to do with the specific number of neural network layers.

Description

technical field [0001] The invention relates to the field of neural network calculations, in particular to a parallel method and device for convolution calculation and data loading of a neural network accelerator. Background technique [0002] Once the neural network appeared, it has become a research hotspot in academia and industry. With the deepening of research, various neural networks have been proposed, including large networks with hundreds of layers in depth and thousands of parameters. . At present, the main research work is done using a graphics processing unit (GPU). The GPU is easy to operate and easy to program. It has inherent advantages for training a neural network, but it also has shortcomings. In terms of executing some reasoning applications, especially large-scale terminal deployment , huge power consumption and high cost. [0003] In March 2016, Google AlphaGo defeated Go world champion and professional nine-dan Go player Li Sedol. Since then, research...

AI Technical Summary

Problems solved by technology

The principle of the existing technology is simple, direct and easy to understand, but it does not fully consider the parallelism between various operations, which makes the reasoning time of large neural networks too long, especially for the target detection neural network with relatively high real-time requirements, the real-time performance becomes worse It will cause missed detection of the network, and then seriously affect the performance

At the same time, due to the lack of parallelism in the existing technology, a large number of convolution kernels need to be stored on-chip in order to ensure the normal calculation, so that the on-chip convolution kernel cache is larger, and then the chip area increases and the cost increases

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