Layout design manufacturing method of integrated circuit
A technology for integrated circuit and layout design, which is applied in the field of layout design and manufacture of integrated circuits, and can solve problems such as affecting the performance of active devices.
Pending Publication Date: 2021-09-10
TAIWAN SEMICON MFG CO LTD
View PDF0 Cites 0 Cited by
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
However, implementing TSVs to form a 3DIC during the fabrication process may result in additional stress distribution on the active region near the TSV, thereby affecting the performance of the active devices in the active region
Method used
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View moreImage
Smart Image Click on the blue labels to locate them in the text.
Smart ImageViewing Examples
Examples
Experimental program
Comparison scheme
Effect test
Embodiment Construction
[0010] The following disclosure provides many different embodiments, or examples, for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are examples only and are not intended to be limiting. For example, the description below that a first feature is formed "on" a second feature or "on" a second feature may include embodiments in which the first and second features are formed in direct contact, as well as embodiments in which Embodiments in which an additional feature may be formed between a first feature and a second feature such that the first feature may not be in direct contact with the second feature. Additionally, this disclosure may reuse reference numbers and / or letters in various instances. Such re-use is for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations disc...
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More PUM
Login to View More Abstract
A layout design manufacturing method of an integrated circuit includes generating an integrated circuit layout design and manufacturing the integrated circuit based on the integrated circuit layout design. Generating an integrated circuit layout design includes: generating a pattern of a first shallow trench isolation region and a pattern of a substrate via region within the first shallow trench isolation region; generating a pattern of a second shallow trench isolation region surrounding the first shallow trench isolation region, the second shallow trench isolation region comprising a first layout region and a second layout region, the second layout region being separated from the first shallow trench isolation region by the first layout region, defining a first active region of a set of dummy devices within the first layout region and a second active region of a set of active devices within the second layout region; and generating a pattern of first gates of a set of dummy devices in the first layout region, each of the first active regions having substantially the same size in the first direction.
Description
technical field [0001] Embodiments of the present invention relate to a layout design of an integrated circuit and its design and manufacturing method, in particular to a layout design of an integrated circuit with substrate through-holes and its design and manufacturing method. Background technique [0002] The semiconductor industry has experienced rapid growth due to the continued increase in the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) in integrated circuit (IC) devices. In large part, this increase in integration density is due to the continued reduction in minimum feature size, which enables more components to be integrated into a given area. In addition to the reduction in minimum feature size, the facilitation of die stacking by using through-substrate vias (TSVs) to form 3-dimensional integrated circuits (3-dimensional ICs, 3DICs) also contributes to increased integration density. However, implement...
Claims
the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More Application Information
Patent Timeline
Login to View More Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02
CPCH01L27/0207G06F30/394H01L23/481H01L27/0886G06F30/392G06F2119/06H01L29/0653
Inventor 胡致嘉陈明发詹森博江孟纬
Owner TAIWAN SEMICON MFG CO LTD