Method and device for shortening erasing time, electronic equipment and storage medium

A technology of erasing time and over-erasing, which is applied in the direction of information storage, static memory, read-only memory, etc., can solve the problems of increasing erasing operation time, uneven distribution of threshold voltage, and many erasing pulses, so as to reduce erasure The effect of erasing time, improving erasure efficiency, and reducing repair time

Pending Publication Date: 2021-09-17
XTX TECH INC
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, if the block address contains one or more sectors that have undergone multiple erasing and programming cycles, the threshold voltage distribution of memory cells in different sectors in this block is different (sectors that have undergone multiple erasing and programming cycles are more It is difficult to be erased, and more erase pulses need to be input), in order to take care of sectors that have undergone multiple erase programming cycles, it is necessary to input more erase pulses to the entire block, which is not necessary for the same block address For a sector that has gone through multiple erase programming cycles, too many input erase pulses are likely to cause over-erase, resulting in a significant increase in over-erase repair time, thereby greatly increasing the overall erase operation time
[0005] For the above problems, there is no effective technical solution

Method used

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  • Method and device for shortening erasing time, electronic equipment and storage medium
  • Method and device for shortening erasing time, electronic equipment and storage medium
  • Method and device for shortening erasing time, electronic equipment and storage medium

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Embodiment Construction

[0039] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all of them. The components of the embodiments of the application generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0040] It should ...

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Abstract

The invention discloses a method and device for shortening erasing time, electronic equipment and a storage medium. The method comprises the following steps: S1, pre-programming storage units in a sector; S2, performing erasing operation on the storage units in the sector; S3, checking the erased sectors, and ignoring the sectors of which the storage units are all successfully erased; S4, repeating the steps S2-S3 until the storage units of all the sectors are erased; and S5, performing over-erasure detection and repair on the storage units in all the sectors; According to the method, the sectors are erased periodically and cyclically, the erased sectors are marked and ignored, and the erased sectors are ignored step by step so as to execute the erasure operation in a targeted manner, so that invalid operation on the erased sectors can be avoided, the erased sectors are effectively prevented from being over-erased, the repair time of over-erasure is shortened, and the erasing efficiency of a NOR Flash chip is improved.

Description

technical field [0001] The present application relates to the field of chip technology, in particular, to a method, device, electronic equipment and storage medium for reducing erasing time. Background technique [0002] The erase operation instructions supported by NOR Flash include chip erase (Chip Erase), block erase (BlockErase), sector erase (Sector Erase), in which a block with a capacity of 64KB is equivalent to 16 sectors with a capacity of 4KB . When a sector within a block address performs multiple erasing and programming cycles (for example, 100K), the threshold voltage (Vth) of the memory cells in this sector will shift to the right, which is reflected in the fact that the erasing speed increases with the number of erasing and programming cycles increase and slow down. [0003] The conventional NOR Flash erasing method is: pre-program the block and then erase together, after erasing, perform erasure verification on the memory cells in the address to be erased (...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/34
CPCG11C16/3468G11C16/3409
Inventor 温靖康蒋丁鲍奇兵王振彪刘梦
Owner XTX TECH INC
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